• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2007.11a
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• pp.81-83
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• 2007

본 논문에서는 다양한 분야에서 응용될 수 있는 아날로그 신호를 디지털 신호로 변환하는 회로를 이용한 전자식 안정기를 구성하였다. 회로의 구성은 온도센서를 이용하여 안정기 ON/OFF 제어를 통한 냉음극 형광램프의 색을 제어하였고 온도센서뿐만 아니라 광센서, 가변저항, 음성센서 등 거의 모든 아날로그 신호의 센서를 사용 할 수 있도록 구성하였다.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.195-202
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• 2004

This paper introduces the design or parallel Pipeline high-speed analog-to-digital converter(ADC) for the high-resolution video applications which require very precise sampling. The overall architecture of the ADC consists of 4-channel parallel time-interleaved 10-bit pipeline ADC structure a]lowing 200MSample/s sampling speed which corresponds to 4-times improvement in sampling speed per channel. Key building blocks are composed of the front-end sample-and-hold amplifier(SHA), the dynamic comparator and the 2-stage full differential operational amplifier. The 1-bit DAC, comparator and gain-2 amplifier are used internally in each stage and they were integrated into single switched capacitor architecture allowing high speed operation as well as low power consumption. In this work, the gain of operational amplifier was enhanced significantly using negative resistance element. In the ADC, a delay line Is designed for each stage using D-flip flops to align the bit signals and minimize the timing error in the conversion. The converter has the power dissipation of 280㎽ at 3.3V power supply. Measured performance includes DNL and INL of +0.7/-0.6LSB, +0.9/-0.3LSB.

• Journal of the Korea Society of Computer and Information
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• v.15 no.4
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• pp.91-98
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• 2010

Advances in communications and control technology, the strengthening of the Internet, and the growing recognition of the urgency to reduce the risk and production cost are motivating the development of improvements in the traditional manufacturing industry. In this paper, we developed a remote dust collector bag control system which is a combination of advanced IT and traditional dust collector based on the event. At first, we made the A/D(Analog/Digital) converter using a micro processor because the differential pressure transmission, which is a sensor of the dust collector, produces analog volt data. A/D converter can provide RS-232 communication to connect with Power Line Communication(PLC) modem. And, n-bytes message format was defined for the efficient dust collector bag information transmission from a dust collector to a user. Also, we designed the data types to model the dust collector and the dust collector bag, and they were logically modeled using XML and object-oriented modeling method. In addition to that, we implemented the system for showing the dust collector bag exchange time exactly to users at real-time using various visual user interfaces.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.157-158
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• 2013

본 논문은 넓은 범위에서 변화하는 입력 전압과 출력 전류 조건에서 동작하는 디지털 제어 방식 공진형 DC-DC 컨버터의 동특성 개선에 대해 기술한다. LLC 직렬 공진형 컨버터의 아날로그 전력 변환단 동특성을 기반으로 150W 디지털 공진형 컨버터 실험보드에 적용하여 아날로그 제어 방식과 디지털 제어방식의 폐루프 성능을 비교한다. 디지털 제어기는 Emulation 방식을 이용하여 설계한다. 제어기 설계의 이론 검증 및 분석은 PSIM Simulation과 실험 측정으로 비교 검증한다.

• Journal of IKEEE
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• v.13 no.1
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• pp.77-86
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• 2009

A wavelet Electrocardiogram(ECG) detector and its analog-to-digital converter(ADC) for low-power implantable cardiac pacemakers are presented in this paper. The proposed wavelet-based ECG detector consists of a wavelet decomposer with wavelet filter banks, a QRS complex detector of hypothesis testing with wavelet-demodulated ECG signals, and a noise detector with zero-crossing points. To achieve high-detection performance with low-power consumption, the multi-scaled product algorithm and soft-threshold algorithm are efficiently exploited. To further reduce the power dissipation, a low-power ADC, which is based on a Successive Approximation Register(SAR) architecture with an on/off-time controlled comparator and passive sample and hold, is also presented. Our algorithmic and architectural level approaches are implemented and fabricated in standard $0.35{\mu}m$ CMOS technology. The testchip shows a good detection accuracy of 99.32% and very low-power consumption of $19.02{\mu}W$ with 3-V supply voltage.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.5
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• pp.403-411
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• 2020

Since the analog circuit of the beta ray sensor circuit for the true random number generator and the power and ground line used in the comparator circuit are shared with each other, the power generated by the digital switching of the comparator circuit and the voltage drop at the ground line was the cause of the decreasein the output signal voltage drop at the analog circuit including CSA (Charge Sensitive Amplifier). Therefore, in this paper, the output signal voltage of the analog circuit including the CSAcircuit is reduced by separating the power and ground line used in the comparator circuit, which is the source of digital switching noise, from the power and ground line of the analog circuit. In addition, in the voltage-to-voltage converter circuit that converts VREF (=1.195V) voltage to VREF_VCOM and VREF_VTHR voltage, there was a problem that the VREF_VCOM and VREF_VTHR voltages decrease because the driving current flowing through each current mirror varies due to channel length modulation effect at a high voltage VDD of 5.5V when the drain voltage of the PMOS current mirror is different when driving the IREF through the PMOS current mirror. Therefore, in this paper, since the PMOS diode is added to the PMOS current mirror of the voltage-to-voltage converter circuit, the voltages of VREF_VCOM and VREF_VTHR do not go down at a high voltage of 5.5V.

• Journal of IKEEE
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• v.22 no.2
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• pp.514-517
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• 2018

In sensor systems, ADC (analog-to-digital converter) demands high resolution, low power consumption, and high signal bandwidth. Sigma-delta ADC achieves high resolution by high order structure and high over-sampling ratio, but it suffers from high power consumption and low signal bandwidth. SAR (successive-approximation-register) ADC achieves low power consumption, but there is a limitation to achieve high resolution due to process mismatch. This paper surveys architecture improvement of ADC to overcome these problems.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.6
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• pp.546-554
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• 2015

Ultra-wideband(UWB) radar is widely used in many penetration radar applications, such as ground-penetrating radar and foliage-penetrating radar, because it has many advantages in detecting concealed objects. One type of UWB radar system is random noise radar, which many be robust to jamming environment. However conventional random noise radar requires high-speed analog-to-digital convertor(ADC) for matched filtering. In this thesis, a pseudo-random noise radar system that maintains anti-jamming characteristics but does not require high-speed ADC is researched. and The UWB system is implemented in a low frequency system, and its performance has been demonstrated by experiment, which proves the concept of the proposed pseudo-random noise radar system.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.512-514
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• 2006

본 논문의 목표는 디지털 방송 수신과 아날로그 방송 수신 및 방송 컨텐츠를 녹화, 저장, 재생이 가능할 뿐만 아니라 각종 멀티미디어 컨텐츠를 즐길 수 있고, 양방향 데이터 방송이 가능하며, 저장된 콘텐트를 스트리밍으로 개인 멀티미디어 플레이어로 스트리밍 이 가능한 다기능 일체형 개인 녹화기를 개발하는 것이다. 고품질 디지털 방송과 기존의 아날로그 방송을 고품질의 디지털 컨텐츠로 변환하여 저장하고, 이를 원하는 시점에 언제든지 볼 수 있을 뿐만 아니라 인터넷 접속하여 어디 서든지 개인 형 멀티미디어 플래이어를 이용하여 스트리밍으로 저장된 컨텐츠를 즐길 수 있다. 이러한 기능을 수행하기 위하여 상당한 성능의 MPU가 필요로 하게 된다. 본 논문에서는 이러한 조건을 만족시키기 위하여 Zoran의 G9Ellite라는 SOC를 채택하였다. 개발된 시스템을 테스트하기 위하여 현재 각 방송사들의 방송을 수신하고 요구된 기능을 테스트 하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.182-185
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• 2014

In this paper, the ADC performs research and development for high speed data transfers to minimize the optical delay. Have more $6{\mu}s$ delay in the data signal converting optical repeater transmission system existing there has been a limit on the high-speed data transmission, and signal conversion. The need to develop a new technique to reduce the delay in time within $2{\mu}s$ data signal converted by using this direct conversion system. It is desired the development of the core technologies necessary for the signal transduction component, such as mobile communications LTE, LTE advanced service transport network is established, the delay time $3{\mu}s$ technology for reducing the delay time in the signal converting a revolutionary step is applied in this paper we have developed an ADC.