• Proceedings of the IEEK Conference
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 Ⅳ
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• pp.1779-1782
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• 2003

본 논문에서는 새로운 색역폭(color gamut) 매핑 방법을 이용하여 디지털 TV 디스플레이 장치의 화질을 개선하는 방법을 제안하였다. 기존에 실시간 적응이 어렵던 색역폭 매핑 방법을 실시간으로 처리하기 위한 하드웨어 구조를 제안하였으며 이를 통하여 수 나노 초 단위의 처리 속도가 필요한 디지털 TV 의 디스플레이 장치에 성공적으로 적용이 가능하였다. 또한 제안된 하드웨어 구조는 필요에 따라 색역폭 매핑 해상도의 조절이 가능하여 해상도 및 하드웨어 구현 비용을 적절히 조절할 수 있는 장점이 있다.

• Journal of Digital Contents Society
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• 제5권3호
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• pp.180-186
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• 2004

XML has an essential funtion of dealing with standardized document to be used in all academic areas and industrial areas as well as e-commerce. The transformation of XML data into Relation Database table is also necessary for data search using SQL language. Mapping relation between XMLand Table in Relation Database is required for transformation of XML. This arti치e studies the mapping relation between XML and Relation Database using DTD which enables to check the unity automatically whenever document is read so that it studied mapping design for the transformation of XML data info Relation Database table.

• Journal of Digital Contents Society
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• 제13권1호
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• pp.37-41
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• 2012

In this paper, we proposed FPGA algorithm for consider the power consumption. Proposed algorithm generated a feasible cluster by circuit partition considering the CLB condition within FPGA. Separated the feasible cluster reduced power consumption using glitch removal method. Glitch removal appled delay buffer insertion method by signal process within the feasible cluster. Also, removal glitch between the feasible clusters by signal process for circuit. The experiments results show reduction in the power consumption by 7.14% comparing with that of [9].

• Journal of Digital Contents Society
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• 제10권4호
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• pp.633-637
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• 2009

In this paper, we present the reuse module library generating algorithm and register-transfer (RT) library generating algorithm considering the power consumption of reuse module for field-programmable gate array (FPGA) technology mapping in order to implement into the circuit for calculating power consumption. To realize the circuit of calculation of power consumption, the FPGA is selected. Considering lookup table (LUT) conditions of selected FPGA, technology mapping process is conducted to minimize the total power consumption. With these information, the circuit is realized using suitable given power consumption among allocated results of modules.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 한국방송∙미디어공학회 2018년도 추계학술대회
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• pp.36-38
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• 2018

본 논문에서는 프로젝터와 카메라를 이용하여 다수의 평면이 결합된 형태의 사물스크린 공간에 디지털 사이니지 서비스를 제공하기 위한 기술을 개발하였다. 연구개발한 기술은 OpenGL 기반의 렌더링 소프트웨어 기반 위에 콘텐츠와 사물스크린 상호간의 기하학적 매핑, 스크린 색상과 주변 조명을 고려한 색상 보정 기능들이 적용되었다. 단순한 객체의 매핑 기능은 사각형과 같은 폴리곤 객체, 복잡한 사물공간 구조는 격자형 매쉬를 이용하여 보정하도록 지원한다. 색상 보정은 스크린으로 활용할 영역이 균일한 색상 특성을 가진 경우에 대응하여 관심 스크린 영역의 영상을 취득하여 컬러 혼합 행렬을 계산하고 이를 보정 S/W와 연동하여 처리되도록 개발했다. 본 연구개발 내용을 통해 향후 임의의 평면을 디지털 사이니지용 디스플레이 공간으로 쉽고 빠르게 활용하기 위한 요소 기술로 활용되기를 기대한다.

• The Journal of the Korea Contents Association
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• 제14권11호
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• pp.620-627
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• 2014

In the contemporary age, social environment has changed from analog to digital. As a media is developed, the public is more familiar to digital than analog. In this society, media art rises as new art. One of the most useful methods in the media art is projection mapping. In this paper, I propose a realization process of artwork 'Cloned Me' that is realized by projection mapping method. Artwork is formed by projecting image contents that are visualized a music on a steel structure. It is different from media facade that the object projected contents has a story composition. It is a strength that the object and contents are connected by story and composition. Also it can be modified each other easily for harmony because the structure is assembly-type. A face that is projected by beam projection is consist of unique structure not fixed rectangular frame. Artwork 'Cloned Me' has significance that it reflects the present age to develop digital cloning.

• The Journal of Engineering Geology
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• 제24권3호
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• pp.343-351
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• 2014

Tunnel face mapping plays an important role in risk analysis and infrastructure support decisions during tunnel construction. In this study, a digital mapping system using a mobile device is employed instead of existing face-mapping methods that rely upon face mapping sheets. The mobile device is then connected to the main server in the field, where a tunnel-specific database is compiled automatically. This information provides real-time feedback on the tunnel face to construction personnel and engineers, thus allowing for rapid assessment of tunnel face stability and infrastructure needs. The Douglas-Peucker algorithm, among others, is employed to resolve problems arising from the detailed mapping and speed problem by data accumulation. This system is expected to raise program optimization through field verification and additional functional improvements.

• Journal of the Institute of Electronics Engineers of Korea SP
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• 제41권5호
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• pp.225-233
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• 2004

A novel real-time color gamut mapping method is described. The color gamut mapping method that is used for enhancing the color reproduction quality between PC monitor and printer devices is adopted for digital TV display quality enhancement. The high definition digital TV display devices operate at the clock speed of around 70MHz ～ 150MHz and permit several nano seconds for real-time gamut mapping. Thus, the concept of three-dimensional reduced resolution look-up table is introduced for real-time processing. The required hardware can be greatly reduced by look-up table resolution adjustment. The proposed hardware architecture is successfully implemented in FPGA and ASIC and also successfully adopted in digital TV display quality enhancement purposes.

• Journal of Digital Contents Society
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• 제14권1호
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• pp.1-5
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• 2013

In this paper a study of efficient CPLD low power algorithm is proposed. Proposed algorithm applicate graph partition method using DAG. Circuit representation DAG. Each nodes set up cost. The feasible cluster create according to components of CPLD. Created feasible cluster generate power consumption consider the number of OR-term, the number of input and the number of output. Implement a circuit as select FC having the minimum power consumption. Compared with experiment [9], and power consumption was decreased. The proposed algorithm is efficient. this paper, we proposed FPGA algorithm for consider the power consumption.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 한국방송∙미디어공학회 2019년도 추계학술대회
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• pp.242-245
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• 2019

실제 인간의 눈이 가장 어두운 물체와 가장 밝은 물체 사이의 차이를 인식하는 동적 영역의 범위는 10¹⁴(cd/㎡)이다. 이를 디지털 영상으로 가능한 최대로 표현하기 위해 HDR 영상을 생성하는 다양한 기술이 개발되었다. 하지만, 기존 디스플레이 장치의 동적 영역은 10³(cd/㎡)로 사람의 동적 영역에 비해 상대적으로 작은 동적 영역을 가진다. 따라서, HDR 영상을 LDR 디스플레이에 효과적으로 표현하기 위해서는 HDR 영상과 시각적으로 유사한 영상을 생성하는 방법인 톤 매핑 기법 (Tone Mapping Operator: TMO)이 필수적이다. 본 논문에서는 HDR 영상을 LDR 디스플레이에 표현하기 위해 개발된 톤 매핑 기법과 톤 매핑 기법의 품질을 평가하는 방법을 소개하고, 각각의 톤 매핑 기법의 품질 점수를 비교한다.