• Journal of the Institute of Electronics Engineers of Korea SP
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• v.37 no.5
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• pp.115-123
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• 2000

In this paper, a block FIR(Finite Impulse Response) filtering architecture is proposed for IF digital down converter. Digital down converter consists of digital mixers. decimation filters and down samplers. In this proposed structure, it is shown that a efficient parallel decimation filter architecture can be produced by cancellation of inherent up sampling of the block filter and following down sampler Furthermore. it is shown that computational complexity of the proposed architecture is reduced by exploiting the block FIR structure and zero values of the digital mixers.

• Proceedings of the IEEK Conference
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• 2000.11d
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• pp.127-130
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• 2000

This paper proposes a low-Power DDC(Digital Down Converters) architecture for IF(Intermediate frequency) signal processing. It is shown that concept of conventional interpolated FIR filters can be expanded to IIR filters for DDC applications. Also in the paper, power dissipations for the proposed architecture and conventional ones are estimated.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2011.11a
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• pp.23-24
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• 2011

아날로그 TV의 디지털화와 마찬가지로 아날로그 라디오 방송의 디지털화도 세계적인 추세이다. DRM(Digital Radio Mondiale)은 송신소의 위치, 방송 지역 및 사용하는 주파수에 따라, 동작모드가 A~E까지 5가지가 있으며, 모드 A~D는 30MHz이하 대역의 디지털 라디오 방송에 사용되는 모드이며, 모드 E는 Band I~II 대역의 디지털 라디오 방송에 사용되는 모드이다. 본 논문에서는 DRM 모드 A~E까지의 신호를 수신 및 분석 가능한 USB 타입 DRM 수신기 구현에 관하여 정리하였다. 대역 필터 및 디지털 다운 컨버터가 DSP를 이용하여 구현되었으며 PC Side에서 DRM 신호를 분석할 수 있도록 설계되었다.

• Journal of the Korea Society of Computer and Information
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• v.17 no.2
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• pp.113-118
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• 2012

In this paper, we discuss the design of the Digital Down Converters for the IEEE 802.11 wireless LAN receiver, which can be used for the customized receiver. The customized receiver can be used for special puropsed services which cannot be realized using the general custom chip. In the OFDM receiver, DDC receives the up sampled Inphase/Quadrature signal from the AD converter and process down sampling and filtering procedures using the Cascaded Intergrator Filter and FIR filters. We discuss the structure and design methodology of DDC's and analyze the simulation results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1219-1225
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• 2001

In this Paper we describe the design of synchronization algorithms for burst QPSK receiver, which are applicable to BWLL uplink. The demodulator consists of digital down converter, matched filter and synchronization circuits. For symbol timing recovery we ufo Gardner algorithm. And we use forth power method and decision directed method for carrier frequency recovery and phase recovery, respectively. For the sake of performance analysis, we compare simulation results with the board implemented by FPGA which is APEX20KE series chip for Alter. The performance results show it works quite well up to the condition that a frequency offset equal to 4.7% of symbol rate.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.307-310
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• 2001

In this paper we describe the design and implementation of uplink receiver for BWLL base station modem. The demodulator consists of digital down converter, matched filter and synchronization circuits. For symbol timing recovery we use Gardner algorithm. And we use forth power method and decision directed method for carrier frequency recovery and phase recovery, respectively. For the sake of performance analysis, we compare simulation results with the board implemented by FPGA which is APEX20KE series chip for Alter. The performance results show it works quite well up to the condition that a frequency offset equal to 4.7% of symbol rate.1

• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.6
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• pp.342-349
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• 2019

We describe and anlayzes the methodology and implementation results of H / W configuration and signal characteristics analysis algorithm for analyzing equipment for analyzing OFDMA physical layer based on 802.16e. Recently, demand for signal analysis of instruments that analyze these signals with the development of digital communication signals is rapidly increasing. Accordingly, it is necessary to develop signal analysis equipment capable of analyzing characteristics of a broadband communication signal using a wideband digital signal processing module. In this paper, we have studied the basic theory of OFDMA in order to devise a device capable of analyzing characterisitcs of broadband communication signals. Second, the structure of OFDMA transmitter/receiver was examined. Third, a wideband digitizer was implemented. we design Wimax signal analysis algorithm based on OFDMA among broadband communication methods and propose Wimax physical layer analysis S/W implementation through I, Q signals. The IF downconverter used the receiver module and the LO generation module of the spectrum analyzer. Quantitative analysis result is obtained through the algorithm of Wimax signal analysis by I, Q data.