• 한국정보교육학회:학술대회논문집
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• 2006.08a
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• pp.109-115
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• 2006

오늘날 IT의 급속한 진보는 사회적, 경제적 변화를 가져왔다. 그리고 많은 나라들이 정보화시대에 선두를 차지하려 노력하고 있다. 이에 미래의 IT산업을 선도할 인재들의 첫 출발점이라고 할 수 있는 초등학교에서의 정보영재교육의 필요성이 더욱 중요시되고 있으며, 현대 디지털 사회 전 분야에 걸쳐 없어서는 안 될 필수적인 요소로 사용되고 있는 디지털 시스템의 동작 원리를 이해하는 것이 요구되고 있다. 이에 디지털 시스템의 동작 원리를 이해하는 데 기초가 되는 디지털 논리 회로에 대한 내용을 초등학교 아동들이 쉽고 흥미롭게 이해할 수 있는 교육방법을 개발하여 실생활에서 필요한 디지털 시스템을 창의적으로 설계하고, 이를 통한 문제해결능력을 향상하고자 한다.

• The Journal of Korean Association of Computer Education
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• v.10 no.6
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• pp.11-18
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• 2007

The proposed virtual laboratory system for digital logic circuits is composed of two main sessions, which are concept-learning session and virtual experiment session by virtual digital kit. During concept-learning session the learners can easily understand the important principles in the digital circuits to be performed. In addition, during virtual laboratory session the virtual experiments are performed by assembling and connecting the circuits on the virtual bread board, applying input voltages, making the output measurements, and comparing and transmitting the virtual experimental data. Every activity done during the virtual laboratory session is recorded on database and will be provided with the learners as a preliminary report form including personal information. Thus, the educators may check out the submitted preliminary report to estimate how well the learners understand the circuit operations. Finally, in order to show the validity of our virtual laboratory system we investigated and analysed the damage rate of real experimental equipment during class and assessed student performance on the five quizzes for one semester.

• Proceedings of the Korean Information Science Society Conference
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• 2001.10a
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• pp.367-369
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• 2001

논리 회로는 하드웨어로 직접 구현할 수도 있으나, 설계된 디지털 논리를 프로그램으로 구현하고 이를 내장형 프로세서가 실행하게 하는 방식으로 구현할 수 있다. 이러한 구현은 내장형 시스템에 적합하도록 코드 크기와 실행 속도가 효율적이어야 한다. 본 논문에서는 복사 전파, 데드코드 삭제, 위상 정렬등의 컴파일러 최적화 기술과 함수 단위 모듈 개념을 도입하여 신호 흐름 분석 기법의 C 코드 자동 발생기를 구현하였다. 회로 시뮬레이션 구현 기법 중 유한 상태 천이 모델 기법으로 코드를 발생하는 Esterel 시스템과 성능 비교 실험을 한 결과, 코드 크기는 평균 84.17%로 감소되었으며 실행 속도는 평균 4.68배로 향상되었다.

• The Journal of Korean Association of Computer Education
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• v.11 no.1
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• pp.23-32
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• 2008

In this paper, we have investigated the education effect of a web-based virtual laboratory for digital logic circuits which consists of multimedia contents about the usages of equipments for logic circuit experiments and the experimental logic circuits. In case of the engineering experiment of the lower grades in universities, preunderstanding about the usages of experimental equipments and the experimental circuits is necessary for the learners to conduct the experiments well. But it is impossible for the learners to have access to the real experimental equipments earlier due to the lack of equipments and the difficulty in management of the equipments. We have implemented the digital logic circuit virtual laboratory which provides the same experimental environment as a real experimental lab, and the learner can conduct the same experiments as the real ones before the real laboratory class. The learners using the laboratory have reduced the experiment completion time by the average of about 8.2% during a term, compared with the learners not using the lab.

• Journal of Internet Computing and Services
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• v.16 no.4
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• pp.61-70
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• 2015

This paper presents a web-based Java applet for understanding the concepts in digital logic circuits and student satisfaction survey was carried out in order to show its educational validity. Through our educational Java applet, the learners will be capable of learning the concepts and principles related to digital logic circuit experiments and how to operate virtual experimental equipments and virtual bread board. The proposed educational Java applet is composed of five important components: Principle Classroom to explain the concepts and principles for digital logic circuit operations, Simulation Classroom to provide a web-based simulator to the learners, Virtual Experiment Classroom to provide interactive Java applet about the syllabus of off-line laboratory class, Assessment Classroom, and Management System. With the aid of the Management System every classroom is organically tied together collaborating to achieve maximum learning efficiency. Finally, we have obtained several affirmative effects such as high learning standard, reducing the total experimental hours and the damage rate for experimental equipments.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.57-65
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• 2014

This paper presents a framework that is based on a reconfigurable macro-model of current-mode logic (CML) high-speed digital circuits enabling equation-based design optimization. The proposed macro-model is compatible with geometric programming, thereby enabling constraint-driven top-level power optimization. The proposed optimization framework is applied to a design of CML based serial-link transmitter with user-defined design specifications as an example of high speed digital circuits using 45nm and 90nm CMOS technology. The proposed optimization framework can derive a design with optimal power efficiency for given transistor technology nodes.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.675-676
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• 2013

This paper presents a design method for multiple-output combinational digital logic systems using time domain based on multiplexing and common multi-terminal extension decision diagrams. The common multi-terminal extension decision diagrams represents extension valued multiple-output functions, while time domain based on multiplexing systems transmit several signals on a single lines. The proposed method can reduce the 1)hardware, 2)logic levels and 3)pins. In the logic system design, we use two types of decision diagrams, that is the common binary decision diagrams and common multi-terminal extension decision diagrams.

• Proceedings of the Korea Multimedia Society Conference
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• 2002.11b
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• pp.587-592
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• 2002

본 논문에서는 De Bruijn 그래프에 기초한 다중처리기구성의 한 가지 방법을 제안하였다. 제안한 방법에서는 유한체상의 수학적 성질과 그래프의 성질을 사용하여 변환연산자를 제한하였으며, 이들 변환연산자를 이용하여 De Bruijn 그래프의 변환표를 도출하였다. 그리고, 이 변환표로부터 유한체상의 De Bruijn 그래프를 도출하였다. 제안한 다중처리기는 유한체상의 임의의 소수와 양의 정수에 대해 구성할 수 있으며 고장허용컴퓨팅시스템, 파이프라인 시스템, 병렬처리 네트워크, 스위칭 함수와 이의 회로, 차세대 디지털논리시스템 및 컴퓨터구조 중의 하나인 다치디지털논리시스템 등에 적용할 수 있으리라 전망된다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.1
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• pp.59-64
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• 2008

In this paper, we developed an virtual lecture to study digital logic circuits. The contents is intended fer the students without or with little knowledge about electrics or electronics. For the beginners, the lecture contains the basic electronics and basic circuit theory as well as the degital logic circuits to be more practical lecture. And we developed the virtual circuit lab which uses real-like devices, circuits and interactive objects for the students to experience practical digital circuits. With the features described above, this contents would be useful for the beginners who want to studying digital logic circuits.

• Journal of Korea Society of Industrial Information Systems
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• v.17 no.4
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• pp.17-23
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• 2012

Ultra low-power design and energy harvesting applications require digital systems to operate under extremely low voltages approaching the point of balance between dynamic and static power consumption which is attained in the sub-threshold operation mode. Delay variations are extremely large in this mode. Therefore, in this paper, a new low-power logic design methodology using asynchronous NCL circuits is proposed to reduce power consumption and not to be affected by various technology variations in nanoscale MOSFET technology. The proposed NCL is evaluated using various benchmark circuits at 0.4V supply voltage, which are designed using 45nm MOSFET predictive technology model. The simulation results are compared to those of conventional synchrouns logic circuits in terms of power consumption and speed.