• Journal of IKEEE
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• v.18 no.1
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• pp.172-178
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• 2014

This paper describes the design technique and the method of analog front-end to measure the saturation of hemoglobin with oxygen sensor. To process the $SpO_2$ value from the sensor, the current data from the sensor should be converted into voltage domain. Designed analog front-end usually converts the current data from the sensor into voltage domain data to pass it on analog-to-digital converter called ADC with a different level of gain characteristics. This circuit was fabricated in a $0.11{\mu}m$ CMOS technology and has 4 level of gain properties. The occupied area is $0.174mm^2$.

• The Journal of the Korea institute of electronic communication sciences
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• v.6 no.2
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• pp.256-261
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• 2011

In this paper, a design and an implementation of an Analog to Digital (A/D) converter are introduced for the conversion of monitored battery cell voltage in the cell voltage monitoring(CVM) system in battery management system(BMS), which is one of the key devices of ECO hybrid cars. The A/D converter in CVM system required a middle conversion speed and a high resolution, therefore, a successive approximate register(SAR) typed A/D converter with 10 bits resolution has been designed and implemented using Magna 0.6um 40V process. The measurement result which kept ${\pm}1$ LSB accuracy in the full scale range(FSR) of 5V, showed the usefulness of the SAR typed A/D converter in realizing a CVM system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.198-204
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• 2001

In this paper, a 3V 8-bit 200MSPS CMOS folding / interpolation A/D Converter is proposed. It employs an efficient architecture whose FR(Folding Rate) is 8, NFB(Number of Folding Block) is 4, and IR (Interpolating Rate) is 8. For the purpose of improved SNDR by to be low input frequency, distributed track and hold circuits are included. In order to obtain a high speed and low power operation, further, a novel dynamic latch and digital encoder based on a novel delay error correction are proposed. The chip has been fabricated with a 0.35${\mu}{\textrm}{m}$ 2-poly 3-metal n-well CMOS technology. The effective chip area is 1070${\mu}{\textrm}{m}$$\times$650${\mu}{\textrm}{m}$ and it dissipates about 230mW at 3.3V power supply. The INL is within $\pm$1LSB and DNL is within $\pm$1LSB, respectively. The SNDR is about 43㏈, when the input frequency is 10MHz at 200MHz clock frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.2
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• pp.323-329
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• 2002

This paper describes an efficient error-compensation technique for designing a low-error truncated Booth multiplier which produces an N-bit output from a two's complement multiplication of two N bit inputs by eliminating the N least-significant bits. Applying the proposed method, a truncated Booth multiplier for area-efficient and low-power applications has been designed, and its performance(truncation error, area) was analyzed. Since the truncated Booth multiplier does not have about half the partial product generators and adders, it results an area reduction of about 35％, compared with no-truncated parallel multipliers. Error analysis shows that the proposed approach reduces the average truncation error by approximately 60％, compared with conventional methods. A 16-b$\times$16-b truncated Booth multiplier core is designed on full-custom style using 0.35-${\mu}{\textrm}{m}$ CMOS technology. It has 3,000 transistors on an area of 330-${\mu}{\textrm}{m}$$\times$262-${\mu}{\textrm}{m}$ and 20-㎽ power dissipation at 3.3-V supply with 200-MHz operating frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.1
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• pp.197-204
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• 2010

This paper proposes a new body-effect compensated switch configuration for low voltage and low distortion switched-capacitor (SC) applications. The proposed circuit allows rail-to-rail switching operation for low voltage SC circuits and has better total harmonic distortion than the conventional bootstrapped circuit by 19 dB. A 2-1 cascaded sigma-delta modulator is provided for performing the high-resolution analog-to-digital conversion on audio codec in a communication transceiver. An experimental prototype for a single-stage folded-cascode operational amplifier (opamp) and a 2-1 cascaded sigma-delta modulator has been implemented m a 0.25 micron double-poly, triple-metal standard CMOS process with 2.7 V of supply voltage. The 1% settling time of the opamp is measured to be 560 ns with load capacitance of 16 pF. The experimental testing of the sigma-delta modulator with bit-stream inspection and analog spectrum analyzing plot is performed. The die size is $1.9{\times}1.5\;mm$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.5C
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• pp.726-736
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• 2004

In this paper, we proposed a new scalar multiplier structure needed for an elliptic curve cryptosystem(ECC) over the standard basis in GF(2$^{163}$ ). It consists of a bit-serial multiplier and a divider with control logics, and the divider consumes most of the processing time. To speed up the division processing, we developed a new division algorithm based on the extended Euclid algorithm. Dynamic data dependency of the Euclid algorithm has been transformed to static and fixed data flow by a localization technique, to make it independent of the input and field polynomial. Compared to other existing scalar multipliers, the new scalar multiplier requires smaller gate counts with improved processor performance. It has been synthesized using Samsung 0.18 um CMOS technology, and the maximum operating frequency is estimated 250 MHz. The resulting performance is 148 kbps, that is, it takes 1.1 msec to process a 163-bit data frame. We assure that this performance is enough to be used for digital signature, encryption/decryption, and key exchanges in real time environments.

• Journal of the Korea Convergence Society
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• v.10 no.12
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• pp.271-280
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• 2019

Smart factory, a critical part of digital transformation, enables data-driven decision making using monitoring, analysis and prediction. Predictive maintenance is a key element of smart factory and the need is increasing. The purpose of this study is to analyze the degradation characteristics of a galvanizing kettle for the steel plating process and to predict the remaining useful life(RUL) for predictive maintenance. Correlation analysis, multiple regression, principal component regression were used for analyzing factors of the process. To identify the trend of degradation, a proposed rolling window was used. It was observed the degradation trend was dependent on environmental temperature as well as production factors. It is expected that the proposed method in this study will be an example to identify the trend of degradation of the facility and enable more consistent predictive maintenance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.16-23
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• 2010

This paper presents 6bit 250MS/s flash A/D converter which can be applied to wireless communication system. To solve the problem of large power consumption in flash A/D converter, control algorithm by input signal level is used in comparator stage. Also, input voltage range detector circuit is used in reference resistor array to minimize the dynamic power consumption in the comparator. Compared with the conventional A/D converter, the proposed A/D converter shows 4.3% increase of power consumption in analog and a seventh power consumption in digital, which leads to a half of power consumption in total. The A/D converter is implemented in a $0.18{\mu}m$ CMOS 1-poly 6-metal technology. The measured results show 106mW power dissipation with 1.8V supply voltage. It shows 4.1bit ENOB at sampling frequency 250MHz and 30.27MHz input frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.3
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• pp.15-20
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• 2012

This paper presents a 5-Gb/s optical receiver circuit realized in a $0.13-{\mu}m$ CMOS technologies for the applications of high-speed digital interface. Exploiting modified RGC input stage at the front-end transimpedance amplifier, interleaving active feedback and source degeneration techniques at the limiting amplifier, the proposed optical receiver chip demonstrates the measured results of $72-dB{\Omega}$ transimpedance gain, 4.7-GHz bandwidth, and $400-mV_{pp}$differential output voltage swings up to the data rate of 5-Gb/s. Also, the chip dissipates 66mW in total from a single 1.2-V supply, and occupies the area of $1.6{\times}0.8mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.17-22
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• 2008

This paper presents a low-power and small-area pulse width modulator by light intensity for photoflash. Light intensity controller is achieved by using capacitor, photodiode, and comparator. The proposed circuit designs digital circuit to reduce static power consumption except comparator. And IGBT driver has short circuit protection using delay cell. The pulse width modulator has the operating range of $V_{MS}$ from 0.5V to 2.5V and pulse width of output from 0.14ms to 1.65ms at 300Hz. The pulse width modulator fabricated in $0.35-{\mu}m$ CMOS technology occupies $0.85mm{\times}0.56mm$. This circuit consumes 3.0mW at 300Hz and 3.0V.