• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.33-38
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• 2011

A novel low-power synchronization technique is presented for the local synchronization. Since the proposed technique transmits an enable signal instead of a clock signal which consumes large power, it can considerably reduce the power consumption. The source-synchronization scheme which is widely adopted for the local synchronization is compared with the proposed technique. It is shown that the proposed low-power synchronization technique provides approximately 50% power saving.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.77-86
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• 2016

This paper describes a dual-mode reference-less CDR(Clock Data Recovery) operating at full / half-rate and its operation algorithm. Proposed reference-less CDR consists of a frequency detector, a phase detector, a charge pump, a loop filter, a voltage controlled oscillator, and a digital block. The frequency and phase detectors operate at both full / half-rate for dual-mode operation and especially the frequency detector is capable of detecting the difference between data rate and clock frequency in the dead zone of general frequency detectors. Dual-mode reference-less CDR with the proposed algorithm can recover the data and clock within 1.2-1.3 us and operates reliably at both full-rate (2.7 Gb/s) and half-rate (5.4 Gb/s) with 0.5-UI input jitter.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.3
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• pp.577-582
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• 2016

The synchronous TDC(Time-to-Digital Converter) of counter-type using current-conveyor is designed by $0.18{\mu}m$ CMOS process and the supply voltage is 3 volts. In order to compensate the disadvantage of a asynchronous TDC the clock is generated when the start signal is applied and the clock is synchronized with the start signal. In the asynchronous TDC the error range of digital output is from $-T_{CK}$ to $T_{CK}$. But the error range of digital output is from 0 to $T_{CK}$ in the synchronous TDC. The error range of output is reduced by the synchronization between the start signal and the clock when the timing-interval signal is converted to digital value. Also the structure of the synchronous TDC is simple because there is no the high frequency external clock. The operation of designed TDC is confirmed by the HSPICE simulation.

• Proceedings of the Korean Information Science Society Conference
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• 2010.06a
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• pp.228-229
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• 2010

• Journal of Korea Multimedia Society
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• v.12 no.3
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• pp.329-334
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• 2009

When an optical disc is being played. the pick-up converts light to analog signal at first. The analog signal is equalized for removing the inter-symbol interference and then the equalized analog signal is converted into the digital signal for extracting the synchronized data and clock signals. There are a lot of algorithms that minimize the BER in extracting the synchronized data and clock when high. density optical disc like BD is being played in low speed. But if the high-density optical disc is played in high speed, it is difficult to adopt the same extraction algorithm to data PLL and PRML architecture used in low speed application. It is because the signal with more than 800MHz should be processed in those architectures. Generally, in the 0.13-${\mu}m$ CMOS technology, it is necessary to have the high speed analog cores and lots of efforts to layout. In this paper, the parallel data PLL and PRML architecture, which enable to process in BD 8x speed of the maximum speed of the high-density optical disc as the extracting data and clock circuit, is proposed. Test results show that the proposed architecture is well operated without processing error at BD 8x speed.

• Journal of the Institute of Convergence Signal Processing
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• v.6 no.4
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• pp.206-211
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• 2005

We describe the design for a correlator and an access code generator in bluetooth system. These are used for a connection setting, a packet decision and a clock synchronization between Bluetooth units. The correlator consists of two blocks; carry save adder based on Wallace tree and threshold-value decision block. It determines on an useful packet and clock-synchronization for input signal of 1.0Mbps through the sliding-window correlating. The access-code generator also consists of two blocks; BCH(Bose-Chadhuri-Hocquenghem) cyclic encoder and control block. It generates the access-codes according to four steps' generation process based on Bluetooth standard. In order to solve synchronization problem, we make use of any memory as a pseudo random sequence. The proposed correlator and access-code generator were coded with VHDL. An FPGA Implementation of these modules and the simulation results are proved by Xilinx chip. The critical delay and correlative margin based on synthesis show the 4.689ns and the allowable correlation-error up to 7-bit.

• ICROS
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• v.4 no.1
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• pp.33-38
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• 1998

이 글에서 언급하듯이 제어분야와 실시간 분야간에는 학제간 연계가 절실히 요구된다. 이에 따라 본 고에서는 분산 실시간 제어 시스템을 개발하는 이들을 위해 핵심적인 실시간 이론들을 소개하였다. 주로 시스템 설계를 위한 이론, 실시간 운영체제, 필드버스를 중심으로 하는 실시간 통신 및 클록 동기화에 대해 기술하였는데 다소 생소한 감도 없지 않다. 하지만 앞으로 실시간 제어 시스템에 대한 관심과 필요가 급격히 증대될 것으로 기대되므로 본 고가 좋은 지침이 되었으면 하는 바이다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.4
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• pp.730-736
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• 2008

We proposed and implemented new DDC system which overcomes the difficulties including lack of flexibility of modifications of frequency which is the problem of previous frequence oscillator and synchronization. New DDC system can create frequence in two decimal points. Moreover, due to its usage in adjusting to frequence clock which is required by many consumers, laser distance instrument can reduce its error; thus, implementation of system is capable of high precision distance measurement can be performed.

• KIPS Transactions on Computer and Communication Systems
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• v.3 no.9
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• pp.293-300
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• 2014

TDMA(Time Division Multiple Access) is a channel access scheme for shared medium networks. The shared frequency is divided into multiple time slots, some of which are assigned to a user for communication. Techniques for TDMA can be categorized into two classes: synchronous and asynchronous. Synchronization is not suitable for small scale networks because it is complicated and requires additional equipments. In contrast, in DESYNC, a biologically-inspired algorithm, the synchronization can be easily achieved without a global clock or other infrastructure overhead. However, DESYNC spends a great deal of time to complete synchronization and does not guarantee the maximum time to synch completion. In this paper, we propose a lightweight synchronization scheme, C-DESYNC, which counts the number of participating nodes with GP (Global Packet) signal including the information about the starting time of a period. The proposed algorithm is mush simpler than the existing synchronization TDMA techniques in terms of cost-effective method and guarantees the maximum time to synch completion. Our simulation results show that C-DESYNC guarantees the completion of the synchronization process within only 3 periods regardless of the number of nodes.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.4
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• pp.239-246
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• 2017

Time synchronization between distributed embedded systems in the Real Time Locating System (RTLS) based on Time Difference of Arrival (TDOA) is one of the most important factors to consider in system design. Clock jitter error between each system causes many difficulties in maintaining such a time synchronization. In this paper, we implemented a system to synchronize clocks between FPGA based distributed embedded systems using the recovery clock of CDR (clock data recovery) used in high speed serial communication to solve the clock jitter error problem. It is experimentally confirmed that the cumulative time error that occurs when the synchronization is not performed through the synchronization logic using the CDR recovery clock can be completely eliminated.