• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.6
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• pp.1081-1086
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• 2008

This paper presents the $3^{rd}$ 4bit sigma delta modulator with the block and timing diagrams of DWA(Data Weighted Averaging) to optimize a operating time. In the modulator, the proposed DWA structure has a stable operation and timing margin so as to remove three latches and another clock. Because the modulator with proposed DWA structure improve timing margin about 23%. It can increase sampling frequency up to 244MHz. Through the MATLAB modeling, the optimized coefficients are obtained to design the modulator. The fully differential SC integrators, DAC, switch, quantizer, and DWA are designed by considering the nonideal characteristics. The designed $3^{rd}$ order 4bit modulator has a power consumption of 40mW and SNR(signal to noise ratio) of 77.2dB under 1.2V supply and 64MHz sampling frequency.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.75-78
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• 2003

In this paper, a second-order 3-bit DSM using DWA(Data Weighted Averaging) algorithm is designed for bluetooth Zero-IF Receiver. The designed circuit has two integrators using a designed OTA, nonoverlapping two-phase clerk generator, 3-bit A/D converter, DWA algorithm and 3-bit D/A converter An ideal model of second-order lowpass DSM with a 3-bit quantizer was configured by using MATLAB, and each coefficients and design specification of each blocks were determined to have 10-bit resolution in 1MHz channel bandwidth. The designed second-order 3-blt lowpass DSM has maximum SNR of 74dB and power consumption is 50mW at 3.3V.

• 한국초전도학회:학술대회논문집
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• v.9
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• pp.48-53
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• 1999

We demonstrate small-scale high-T$_c$ superconductor RSFQ(Rapid Single Flux Quantum) circuits using multilayer bicrystal technology. An RSFQ balanced comparator is demonstrated with good current resolution, and its operating conditions are discussed in some detail. A single-loop delta-sigma modulator is realized adding a feedback loop to the comparator. The effect of the feedback is confirmed by dc measurement and simulation. A design of an RSFQ toggle flip-flop with the same multilayer bicrystal technology is suggested.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.5
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• pp.808-815
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• 1990

This paper treats with the design method for the single loop oversampled Sigma-Delta A/D converter with one delay and the digital integrator. Such an integrator was kgenerated by means of the bilinear transform of the analog integrator. The frequency spectrums of the quantizer and the decimator output signal are evaluated by FFT respectively. With the performance evaluation system, the values of SNR are obtained versus the input sinusoidal signal amplitude, frequency, the oversampling ratio, the DC-input level, the loop gain and the limitting value of the integrator. As compared with existing results, values of SNR versus the input signal amplitude and the oversampling ratio for the suggested system are about 6dB higher then previously reported results respectively. Furthermore, this approach achieves an about 60dB input dynamic range.

• 전자공학회논문지 IE
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• v.46 no.1
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• pp.1-6
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• 2009

This paper presents the digital PLL architecture and design for improving the frequency detection range and locking time for wide-band frequency synthesizer applications. In this research, a wide-range digital logic quadricorrelator is used for wide-band and fast frequency detector and sigma-delta modulator with 2-bit up-down counter is adopted for DCO control. The proposed digital PLL reduces the phase noise from quantization effect and is suitable for implementation of wide-band fast-locking as well as low power features, which is in high demand for mobile multimedia applications.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.609-610
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• 2008

In this paper, a 110 dB, 1.024 MHz fourth-order single-loop Delta-Sigma sigma modulator has been presented with an over-sampling ratio of 128 and an overload factor of -6 dB for a bandwidth of 4 kHz. In particular, this ${\Sigma}-{\Delta}$ modulator is well suited for high accuracy measure systems. The whole modulator consumes only 3-mW from a single 3.3V supply in a $0.35-{\mu}m$ CMOS technology.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.437-438
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• 2008

This paper proposes a 8th-order single loop band-pass sigma-delta modulator that satisfies a wide bandwidth of 6MHz, which is required for a HDTV application. The proposed architecture is based on a simple analog structure that enlarges the noise shaping with a low OSR. In addition, a feedforward scheme is used to relax op-amp performance requirements. The proposed modulator has been simulated using the 0.18um 1.8v TSMC technology. The simulation results show that the bandwidth is 6MHz and SNQR is 70dB.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.152-155
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• 2000

Oversampling modulators based on high-order sigma-delta modulation provide an effective means of achieving high-resolution A/D conversion in a VLSI technology. Because high-order noise shaping great]y reduces the quantization noise in the signal band. This paper introduces a third-order cascaded sigma-delta modulator that is stable for large input level. Modulator was simulated 3.3V single power supply voltage in 0.65$\mu\textrm{m}$ CMOS technology. It achieves 80㏈ SNR for a 20㎑ input signal bandwidth. A lock frequency is 3㎒ that is 80 oversampling ratio.

• Journal of IKEEE
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• v.17 no.3
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• pp.248-253
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• 2013

Frequency detector is a circuit that converts the frequency to a digital representation and finds its application in various fields such as modulator and synchronization circuitry. In this paper, a couple of first-order and second-order frequency discriminator structures are modeled and analyzed with their quantization noise sources. Also a delta-sigma frequency detector architecture is proposed. Through theoretical analysis and derived equations, the output noise is obtained, which is validated by simulation. The proposed all-digital frequency discriminator may be applied in the feedback path of the all-digital phase-locked loop.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.982-985
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• 1999

An efficient technique to trade off speed for resolution is the sigma-delta modulation (SDM). This paper proposes a new SDM architecture to improve conversion rates and SNR(Signal-to Noise Ratio) by using master clock and four divided clock. The charateristics of the proposed SDM are simulated in MATLAB environment. and optimizing the capacitor sizes is done by iterative processing. other analog characteristics are simulated using 0.65${\mu}{\textrm}{m}$ n-well CMOS process, double poly and single metal. The result of simulation shows that more increasing the effective bits of internal ADC/DAC, bigger the improvement of SNR.