• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.568-573
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• 2002

In this paper, the Viterbi decoder containing new branch metrics of the squared Euclidean distance with multiple order phase differences is introduced in order to improve the bit error rate (BER) in the differential detection of the trellis-coded MDPSK-OFDM. The proposed Viterbi decoder is conceptually same as the Continuous multiple phase differential detection method that uses the branch metric with multiple phase differences. Also, we describe the Viterbi algorithm in order to use this branch metrics. Our study shows that such a Viterbi decoder improves BER performance without sacrificing bandwidth and power efficiency Also. the proposed algorithm ran be used in the single carrier modulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2444-2450
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• 2011

In this paper, we propose the low fractional spur phase-locked loop(PLL) with multiple phase-frequency detector(PFD). The fractional spurs are suppressed by using a new PFD. The new PFD architecture with two different edge detection methods is used to suppress the fractional spur by limiting a maximum width of the output signals of PFD. The proposed PLL was simulated by HSPICE using a 0.35m CMOS parameters. The simulation results show that the proposed PLL is able to suppress fractional spurs with fast locking.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.74-86
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• 2002

This paper proposes a VLSI architecture for high-speed data processing of the differential phase detectors with the decision feedback. To improve the BER performance of the conventional differential phase detection, DF-DPD, DPD-RGPR and DFDPD-SA have been proposed. These detection methods have the architecture feedbacking the detected phase to reduce the noise of the previous symbol as phase reference. However, the feedback of the detected phase results in lower data processing speed than that of the conventional differential phase detection. In this paper, the VLSI architecture was proposed for high-speed data processing of the differential phase detectors with decision feedback. The Proposed architecture has the pre-calculation method to previously calculate the results on 'N'th step at 'M-1'th step and the pre-decision feedback method to previously feedback the predicted phases at 'M-1'th step. The architecture proposed in this paper was implemented to RTL using VHDL. The simulation results show that the Proposed architecture obtains the high-speed data processing.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2011.06a
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• pp.331-333
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• 2011

GNSS를 이용한 위치 결정은 육상, 항만 및 해양 등의 많은 분야에서 공적 상업적인 목적으로 많이 연구되고 있다. 최근 코드 측정치 분해능이 한계를 가지는 것을 인지하고 반송파 위상 측정치를 이용한 위치 결정에 많은 관심을 가진다. 반송파 위상 측정치는 데이터 수집 환경에 의해서 코드 측정치보다 치명적인 영향을 받아 미지정수 결정과 별개로 반송파 위상 측정치 모니터링에 대한 연구가 필요하다. 반송파 위상 측정치는 다중경로, 수신기 내부 문제 등으로 인하여 Cycle-slip, Half Cycle과 같은 반송파 위상 측정치 이상 현상이 발생한다. 특히, Cycle-slip 현상은 반송파 위상 측정치의 바이어스 성분으로 사용자의 위치 결정에 악영향을 미친다. 본 논문에서는 Cycle-slip 현상에 대해서 설명하고, 기존에 연구된 Cycle-slip 현상에 대한 검출, 결정 및 확인 기법들의 장단점을 비교하였다. 마지막으로 시뮬레이션 기반의 Cycle-slip 검출, 결정 및 확인 기법들의 성능을 비교 분석하였다.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.2
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• pp.46-52
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• 2014

This paper presents a multiple gain controlled digital phase and frequency detector with a fast lock-time. Lock-time of the digital PLL can be significantly reduced by applying proposed adaptive gain control technique. A loop gain of the proposed digital PLL is controlled by three conditions that are very large phase difference between reference and feedback signal, small phase difference and before lock-state, and after lock-state. The simulation result shows that lock-time of the proposed multiple gain controlled digital PLL is 100 times faster than that of the conventional structure with unit gain mode.

• The Journal of the Korea Contents Association
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• v.10 no.2
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• pp.72-80
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• 2010

The 1Gbps clock and data recovery (CDR) circuit using the proposed multi-point phase detector (PD) is presented. The proposed phase detector generates up/down signals comparing 3-point that is data transition point and clock rising/falling edge. The conventional PD uses the pulse width modulation (PWM) that controls the voltage controlled oscillator (VCO) using the width of a pulse period's multiple. However, the proposed PD uses the pulse number modulation (PNM) that regulates the VCO with the number of half clock cycle pulse. Therefore the proposed PD can controls VCO preciously and reduces the jitter. The CDR circuit is tested using 1Gbps $2^{31}-1$ pseudo random bit sequence (PRBS) input data. The designed CDR circuit shows that is capable of recovering clock and data at rates of 1Gbps. The recovered clock jitter is 7.36ps at 1GHz and the total power consumption is about 12mW. The proposed circuit is implemented using a 0.18um CMOS process under 1.8V supply.

• The Journal of the Acoustical Society of Korea
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• v.32 no.1
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• pp.71-78
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• 2013

This paper describes a multiple audio watermarking using Quantization Index Modulation (QIM) on frequency phase and magnitude response. Proposed embedding procedure is composed of two stage. At the first stage, the watermark is embedded on the frequency phase response using QIM. In the second stage, the watermark is embedded using adaptive QIM with the step-size that is adaptively determined using the maximum value of the frequency magnitude response of every frame. The watermark is extracted by calculating the Euclidean distance as the blind detection. The proposed method is robust against most of attacks of audio watermark benchmarking. For the Fourier attacks, the proposed method shows over 95% recovery rate.

• Journal of Advanced Navigation Technology
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• v.16 no.4
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• pp.593-601
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• 2012

This paper develops and analyzes a new multiple-hypothesis Receiver Autonomous Integrity Monitoring (RAIM) algorithm as a candidate for future standard architecture. The proposed algorithm can handle simultaneous multiple failures as well as a single failure. It uses measurement residuals and satellite observation matrices of several consecutive epochs for Failure Detection and Exclusion (FDE). The proposed algorithm redueces the Minimum Detectable Bias (MDB) via the Relative RAIM (RRAIM) scheme. Simulation results show that the proposed algorithm can detect and filter out multiple failures in tens of meters.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.2242-2244
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• 2000

시분할 다중화 방식을 이용한 정전 구동형 XY 스테이지의 새로운 위치 검출 방법을 제안한다. 각축의 고정자에 90도의 위상차를 가지는 여기(excitation) 신호를 주입하여 스테이지와 연결된 1개의 charge amplifier와 S/H를 이용하여 x축과 y축 방향의 위치를 검출한다. charge amplifier의 파라미터는 DC 이득이 크고 또한 신호간 간섭이 발생하지 않도록 설정한다. 제안된 방법은 XY 스테이지의 디지털 서보 제어기의 구성요소인 S/H를 사용하기 때문에 기존의 방식과는 달리 위치 신호의 검출이 안정적이고 반송 신호에 의한 고조파 왜곡과 복조 과정에서 발생되는 지연을 현저히 줄일 수 있으며 간단하게 구현할 수 있다.

• Journal of IKEEE
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• v.22 no.3
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• pp.800-804
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• 2018

This paper presents a novel HF band differential quadrature phase-shift keying (DQPSK) orthogonal frequency-division multiplexing (OFDM) communication system. The system can deliver 3.6 kbps with a bandwidth of about 3 kHz. In a digital modem, OFDM with 32-point fast Fourier transform is used. In the system, each subcarrier uses DQPSK modulation. Hence, a demodulator does not require carrier phase recovery and symbol timing recovery. And, each subcarrier employs CRC error check code individually. By using CRC code for each subcarrier, bit error caused by multipath fading can be recovered simply.