• Title/Summary/Keyword: 다중 링 구조

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ECG Compression Structure Design Using of Multiple Wavelet Basis Functions (다중웨이브렛 기저함수를 이용한 심전도 압축구조설계)

  • Kim Tae-hyung;Kwon Chang-Young;Yoon Dong-Han
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.9 no.3
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    • pp.467-472
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    • 2005
  • ECG signals are recorded for diagnostic purposes in many clinical situations. Also, In order to permit good clinical interpretation, data is needed at high resolutions and sampling rates. Therefore In this paper, we designed to compression structure using multiple wavelet basis function(SWBF) and compared to single wavelet basis function(SWBF) and discrete cosine transform(DCT). For experience objectivity, Simulation was performed using the arrhythmia data with sampling frequency 360Hz, resolution lIbit at MIT-BIH database. An estimate of performance estimate evaluate the reconstruction error. Consequently compression structure using MWBF has high performance result.

A study of QoS for High Speed MIOQ Packet Switch (다중 입출력 큐 방식 고속 패킷 스위치를 위한 QoS에 대한 연구)

  • Ryu, Kyoung-Sook;Choe, Byeong-Seog
    • Journal of Internet Computing and Services
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    • v.9 no.2
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    • pp.15-23
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    • 2008
  • This paper proposes the new structural MOQ(Multiple Input/Output-Queued) switch which guarantees QoS while maintaining high efficiency and deals with the Anti-Empty algorithm which is new arbitration algorithm to be used for the proposed switch. The new structure of the proposed switch based on MIQ, MOQ is designed to have the same buffer speed as the external line speed. Also, the proposed switch makes it possible to remove the weak point of existing methods and introduces the new method of the MOQ operation to support QoS. Therefore, this switch is equal to the Output Queued switch in efficiency and delay, and guarantees the high-speed switching supporting QoS without cell loss.

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Design and Implementation of Real Time Device Monitoring and History Management System based on Multiple devices in Smart Factory (스마트팩토리에서 다중장치기반 실시간 장비 모니터링 및 이력관리 시스템 설계 및 구현)

  • Kim, Dong-Hyun;Lee, Jae-min;Kim, Jong-Deok
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.25 no.1
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    • pp.124-133
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    • 2021
  • Smart factory is a future factory that collects, analyzes, and monitors various data in real time by attaching sensors to equipment in the factory. In a smart factory, it is very important to inquire and generate the status and history of equipment in real time, and the emergence of various smart devices enables this to be performed more efficiently. This paper proposes a multi device-based system that can create, search, and delete equipment status and history in real time. The proposed system uses the Android system and the smart glass system at the same time in consideration of the special environment of the factory. The smart glass system uses a QR code for equipment recognition and provides a more efficient work environment by using a voice recognition function. We designed a system structure for real time equipment monitoring based on multi devices, and we show practicality by implementing and Android system, a smart glass system, and a web application server.

Packet Scheduling Scheme for Multiple Switches in SDN Environment (SDN 환경에서 다중 스위치를 위한 패킷 스케줄링 기법)

  • Lim, Hwan-Hee;Yoo, Seung-Eon;Lee, Byung-Jun;Kim, Kyung-Tae;Youn, Hee-Yong
    • Proceedings of the Korean Society of Computer Information Conference
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    • 2019.01a
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    • pp.93-94
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    • 2019
  • 최근 클라우드 서비스가 급속도로 등장하고 있으며 이러한 서비스는 기존의 IP 네트워크를 사용한다. 기존의 네트워크는 댜앙한 트래픽 패턴에 대해 비 효율적이고 복잡한 구조를 가지고 있는 문제가 있다. 이러한 문제를 해결하기 위해 SDN 기술이 도입되어 널리 보급되고 있다. 클라우드 서비스 센터에서는 SDN 기술을 채택하여 많은 성과를 이루고 있지만 패킷 스케줄링 같은 분야는 아직 초기단계이다. 또한 SDN 환경에서 각 네트워크 노드로부터 데이터와 관련된 스위치에 효율적으로 전달하는 것이 중요한 이슈로 부각되고 있으며 본 논문에서는 큐잉이론을 적용한 패킷 스케줄링 기법을 제안한다.

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High-Performance Line-Based Filtering Architecture Using Multi-Filter Lifting Method (다중필터 리프팅 방식을 이용한 고성능 라인기반 필터링 구조)

  • 서영호;김동욱
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.8
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    • pp.75-84
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    • 2004
  • In this paper, we proposed an efficient hardware architecture of line-based lifting algorithm for Motion JPEG2000. We proposed a new architecture of a lifting-based filtering cell which has an optimized and simplified structure. It was implemented in a hardware accommodating both (9,7) and (5,4) filter. Since the output rate is linearly proportional to the input rate, one can obtain the high throughput through parallel operation simply by adding the hardware units. It was implemented into both of ASIC and FPGA The 0.35${\mu}{\textrm}{m}$ CMOS library from Samsung was used for ASIC and Altera was the target for FRGA. In ASIC, the proposed architecture used 41,592 gates for the lifting arithmetic and 128 Kbit memory. For FPGA it used 6,520 LEs(Logic Elements) and 128 ESBs(Embedded System Blocks). The implementations were stably operated in the clock frequency of 128MHz and 52MHz, respectively.

Design of Multi-FPNN Model Using Clustering and Genetic Algorithms and Its Application to Nonlinear Process Systems (HCM 클러스처링과 유전자 알고리즘을 이용한 다중 FPNN 모델 설계와 비선형 공정으로의 응용)

  • 박호성;오성권;안태천
    • Journal of the Korean Institute of Intelligent Systems
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    • v.10 no.4
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    • pp.343-350
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    • 2000
  • In this paper, we propose the Multi-FPNN(Fuzzy Polynomial Neural Networks) model based on FNN and PNN(Polyomial Neural Networks) for optimal system identifacation. Here FNN structure is designed using fuzzy input space divided by each separated input variable, and urilized both in order to get better output performace. Each node of PNN structure based on GMDH(Group Method of Data handing) method uses two types of high-order polynomials such as linearane and quadratic, and the input of that node uses three kinds of multi-variable inputs such as linear and quadratic, and the input of that node and Genetic Algorithms(GAs) to identify both the structure and the prepocessing of parameters of a Multi-FPNN model. Here, HCM clustering method, which is carried out for data preproessing of process system, is utilized to determine the structure method, which is carried out for data preprocessing of process system, is utilized to determance index with a weighting factor is used to according to the divisions of input-output space. A aggregate performance inddex with a wegihting factor is used to achieve a sound balance between approximation and generalization abilities of the model. According to the selection and adjustment of a weighting factor of this aggregate abjective function which it is acailable and effective to design to design and optimal Multi-FPNN model. The study is illustrated with the aid of two representative numerical examples and the aggregate performance index related to the approximation and generalization abilities of the model is evaluated and discussed.

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A Ring-Based Multiprocessor System using a New Snooping Protocol (새로운 스누핑 프로토콜을 사용한 링 구조의 다중 프로세서 시스템)

  • Jeong, Seong-U;Kim, Hyeong-Ho;Jang, Seong-Tae;Jeon, Ju-Sik
    • Journal of KIISE:Computer Systems and Theory
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    • v.26 no.3
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    • pp.313-323
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    • 1999
  • 현재 컴퓨터 시장에서는 버스에 기반한 시스템이 주류를 이루고 있다. 프로세서의 속도가 매우 빠른 속도로 증가하고 있기 때문에 버스는 병목현상을 일으키고 , 버스의 속도는 불완전한 전송선의 한계로 인해서 제한된다. 시스템 연구자들은 버스를 고속의 단방향 지점간 링크(point-to-point link)를 사용해서 대체하려고 하고 있다. 이 논문에서 새로운 링 구조의 시스템(PANDA)을 제안하고,이 시스템에 적합한 스누핑 캐쉬 일관성 프로토콜을 제사한다. 또한 제안된 시스템은 SCI 캐쉬 일관성 프로토콜을 채택하는 시스템의 네트워크 인터페이스를 수정함으로써 쉽게 구현될 수 있는 이점을 지닌다. 확률적 모델링과 program-driven simulator를 이용하여 제안된 시스템과 full map 디렉토리 프로토콜을 사용하는 시스템과 스누핑 프로토콜을 사용하는 슬롯 링 시스템(Express Ring)을 분석하였다. 실험의 결과로 제안된 시스템은 부가적 하드웨어가 필요한 full map 디렉토리 시스템에 비해서 대등한 성능을 지니고 슬롯링 시스템에 비해서는 29%까지의 성능향상을 보인다.

An Area-Efficient DC-DC Converter with Poly-Si TFT for System-On-Glass (System-On-Glass를 위한 Poly-Si TFT 소 면적 DC-DC 변환회로)

  • Lee Kyun-Lyeol;Kim Dae-June;Yoo Changsik
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.2 s.332
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    • pp.1-8
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    • 2005
  • An area-efficient DC-DC voltage up-converter in a poly-Si TFT technology for system-on-glass is described which provides low-ripple output. The voltage up-converter is composed of charge-pumping circuit, comparator with threshold voltage mismatch compensation, oscillator, buffer, and delay circuit for multi-phase clock generation. The low ripple output is obtained by multi-phase clocking without increasing neither clock frequency nor filtering capacitor The measurement results have shown that the ripple on the output voltage with 4-phase clocking is 123mV, while Dickson and conventional cross-coupled charge pump has 590mV and 215mV voltage ripple, respectively, for $Rout=100k\Omega$, Cout-100pF, and fclk=1MHz. The filtering capacitor required for 50mV ripple voltage is 1029pF and 575pF for Dickson and conventional cross-coupled structure, for Iout=100uA, and fclk=1MHz, while the proposed multi-phase clocking DC-DC converter with 4-phase and 6-phase clocking requires only 290pF and 157pF, respectively. The efficiency of conventional and the multi-phase clocking DC-DC converter with 4-phase clocking is $65.7\%\;and\;65.3\%$, respectively, while Dickson charge pump has $59\%$ efficiency.

A WDM Based Multichannel All-Optical Ring Network (파장 분할 다중화에 의한 다 채널 광 링 통신망의 성능 분석)

  • 박병석;강철신;신종덕;정제명
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.19 no.1
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    • pp.159-169
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    • 1994
  • A multichannel optical slotted ring network is designed using a wavelength division multiplexing(WDM) technique and photonic packet switching devices. The electronics speed bottleneck is removed out of the ring, which allows utilization of the full bandwidth for the optical fiber transmission medium. The ring channel adopts a slotted ring concept with a destination cell remove strategy for the eing access mechanism. The slot size in the ring is selected as the same as that of ATM based cell in order to be used as B-ISDN Access Networks. In this paper, we devised a mathematical method to measure the average transfer delay characteristics of the network. The analytical method turned out to yield accurate results over a broad range of parameters in comparison to simulation results. From the study, we observed the average transfer delay of the network as the network parameters vary.

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Reliability Evaluation of Fiber Optic Sensors Exposed to Cyclic Thermal Load (주기적인 반복 열하중에 노출된 광섬유 센서의 신뢰성 평가)

  • Kim, Heon-Young;Kang, Donghoon;Kim, Dae-Hyun
    • Journal of the Korean Society for Nondestructive Testing
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    • v.36 no.3
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    • pp.225-230
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    • 2016
  • Fiber Bragg grating (FBG) sensors are currently the most prevalent sensors because of their unique advantages such as ease of multiplexing and capability of performing absolute measurements. They are applied to various structures for structural health monitoring (SHM). The signal characteristics of FBG sensors under thermal loading should be investigated to enhance the reliability of these sensors, because they are exposed to certain cyclic thermal loads due to temperature changes resulting from change of seasons, when they are applied to structures for SHM. In this study, tests on specimens are conducted in a thermal chamber with temperature changes from -$20^{\circ}C$ to $60^{\circ}C$ for 300 cycles. For the specimens, two types of base materials and adhesives that are normally used in the manufacture of packaged FBG sensors are selected. From the test results, it is confirmed that the FBG sensors undergo some degree of compressive strain under cyclic thermal load; this can lead to measurement errors. Hence, a pre-calibration is necessary before applying these sensors to structures for long-term SHM.