• Korean Journal of Optics and Photonics
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• v.11 no.5
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• pp.330-334
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• 2000

A new pha~e lock loop (PLL) IS proposed and demonstrated fat clock recovery from 40 Gblt/s time-dIvision-multiplexed (TDM) optical pulse tri.lin, The proposed clock lecovery scheme lmproves the Jitter effecl cOlmng from the clock. pulse laser of harmonically-mode locked flber laser The cross-corrdation frequency component between the optical Signa] and an optical clock pulse tram is deteCled as a fonr-wave-mixing (FWM) SIgnal generated in SOA. The lock-in freqnency range of the clod. recovery IS found to be within 10 KHz. 0 KHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.8A
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• pp.779-785
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• 2002

This paper presents a phase-based stereo matching algorithm in order to efficiently extract 3-dimensional objects from two 2D images. Conventional phase-based methods, especially using windowed Fourier phases, inherit good properties in the case of hierarchical approaches, because they basically use a multi-resolution phase map. On the contrary, their computational costs are very heavy. Therefore, a fast hierarchical approach, using multi-resolution phase-based strategy and reducing the redundancy of phase calculations, is proposed in this pare. In addition, a structural matching algorithm on the phase domain is adopted to improve the matching quality. In experimental results, it is shown that the computation loads are considerably reduced about 8 times and stable outputs are obtained.

• The Journal of the Acoustical Society of Korea
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• v.29 no.4
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• pp.229-236
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• 2010

Phase coherent modulation techniques in underwater acoustic channel can improve bandwidth efficiency and data reliability, but they are made difficult by time-varying intersymbol interference. This paper proposes an adaptive equalizer combined with phase estimator which compensates distortions caused by time-varying multipath and phase variation. The experiment in the East sea demonstrates phase coherent signals are distorted by time-varying multipath propagation and the proposed scheme equalizes them. Bit error rate of BPSK and QPSK are 0.0078 and 0.0376 at 300 meter horizontal distance and 0.0146 and 0.0293 at 1000 meter respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.13-22
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• 2010

This paper proposed the dual-loops multiphase DLL based mixed VCO/VCDL for a high frequency phase noise suppression of the input clock and the multiple frequencies generation with a precise duty cycle. In the proposed architecture, the dual-loops DLL uses the dual input differential buffer based nMOS source-coupled pairs at the input stage of the mixed VCO/VCDL. This can easily convert the input and output phase transfer of the conventional DLL with bypass pass filter characteristic to the input and output phase transfer of PLL with low pass filter characteristic for the high frequency input phase noise suppression. Also, the proposed DLL can correct the duty-cycle error of multiple frequencies by using only the duty-cycle correction circuits and the phase tracking loop without additional correction controlled loop. At the simulation result with $0.18{\mu}m$ CMOS technology, the output phase noise of the proposed DLL is improved under -13dB for 1GHz input clock with 800MHz input phase noise. Also, at 1GHz operating frequency with 40%~60% duty-cycle error, the duty-cycle error of the multiple frequencies is corrected under $50{\pm}1%$ at 2GHz the input clock.

• The Bulletin of The Korean Astronomical Society
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• v.37 no.2
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• pp.157.1-157.1
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• 2012

1990년대 제안된 RTK(Real-Time Kinematics)는 GNSS/GPS 반송파 위상(carrier phase) 관측값을 이용한 방식으로 cm 수준의 정확도를 실시간으로 산출할 수 있어 측지 측량 등 다양한 분야에서 활용되고 있다. 그러나 한 가지 중요한 단점은 이 방식을 사용하는 기준국과 사용자는 10~20km 이내에 존재해야만 빠르고 신뢰할 수 있는 해를 산출할 수 있다는 점이다. 이는 궤도오차, 대류층 및 전리층 오차에 공간 상관성(spatially correlated) 있기 때문인데, 사용자 주변을 둘러싼 다중 기준국들의 측정치를 조합하여 보상하거나 모델링하여 줄이는 방식인 다중 기준국 네트워크 기반의 RTK 알고리즘이 제안되어 사용되고 있다. 다중 기준국 네트워크 기반의 RTK 프로세스에서 기준국간 미지정수 결정은 전 과정의 핵심 프로세스라고 할 수 있으며, 관련되어 많은 기술들이 제안되고 연구되어 왔다. 특히, 1980년대 말부터 현재까지 후처리 기반으로 꾸준하게 연구되고 있는 Blewitt에 의해 전리층 제거 조합과 Wide-lane 반송파 위상 조합을 활용한 미지정수 검색 방법이 대표적이며 이후에도 Gao, Colombo등 다양한 연구자에 의해 활용되었다. 이 연구에서는 실시간으로 다중 기준국 반송파 미지정수를 결정하는 기술에 대한 연구를 수행하였다. L1, L2 관측값 조합으로 인한 관측값의 잡음 수준이 증가하는 영향을 피하기 위해 L1, L2 반송파 위상 및 의사거리를 그대로 관측값으로 사용하여 사용자 위치 및 속도, 기준국간 이중 차분된 전리층 지연 수직성분, 대류층 wet 지연 수직 성분, 이중 차분된 미지정수를 미지의 상태변수로 확장 칼만필터를 통해 직접적으로 추정하는 방식으로 미지정수의 실수해를 결정하였고, 정수해는 실시간에 적합한 MLAMBDA 기법과 비율테스트를 통한 정수해 검정기법을 통해 결정하였다.

• Journal of IKEEE
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• v.10 no.1 s.18
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• pp.16-21
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• 2006

This paper shows a vernier delay technique for generating precise multiphase clocks using PLL structure. The proposed technique can achieve the finer timing resolution less than the gate delay of the delay chain in VCO. Using this technique, 62.5ps of timing resolution can be achieved if the reference clock rate is set at 1GHz using 0.18um CMOS technology. Jitter of 14ps peak-to-peak was measured.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.183-184
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• 2012

본 논문에서는 출력 인덕터 리플과 2차 측 정류기의 공진 전압을 저감할 수 있는 다중 위상천이 풀 브리지 컨버터를 제안한다. 제안된 회로는 총 8개의 스위치가 사용되며, 각 4개의 스위치가 하나의 위상천이 풀 브리지 인버터 부를 구성하는 구조이다. 기존 위상천이 풀 브리지 컨버터의 경우, 진상레그와 지상레그의 위상차이를 조절하여 출력전압을 제어하는데 반해, 제안된 회로는 진상레그와 지상레그의 위상차이 뿐만 아니라 각 풀 브리지 인버터 부의 위상차이를 동시에 조절하여 출력전압을 제어하는 것이 특징이다. 이를 통하여 제안회로는 출력 인덕터 전류 리플 및 2차 측정류기의 공진 전압을 크게 저감시킬 수 있어 고 효율화에 유리하다. 본 논문에서는 제안된 회로의 이론적 해석 및 PSIM 모의실험을 수행하며, 450W급 시작품을 제작하여 제안회로의 타당성을 검증하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2409-2418
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• 2013

Two frequency synthesizers are proposed to generate a clock for a sub-sampler of an on-chip oscilloscope in this paper. These proposed frequency synthesizers are designed by using a multi-phase delayed-locked loop (DLL)-based phase selector and a fractional-N phase-locked loop (PLL), and they are analyzed by comparing simulation results of each frequency synthesizer. Two proposed frequency synthesizers are designed using a 65-nm CMOS process with a 1V supply and output the clock with the frequency of 121.15 MHz when the frequency of an input clock is 125 MHz. The designed frequency synthesizer using a multi-phase DLL-based phase selector has the area of 0.167 $mm^2$ and the peak-to-peak jitter performance of 2.88 ps when it consumes the power of 4.75 mW. The designed frequency synthesizer using a fractional-N PLL has the area of 0.662 $mm^2$ and the peak-to-peak jitter performance of 7.2 ps when it consumes the power of 1.16 mW.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.5
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• pp.907-916
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• 2019

In this paper, we propose a new five-qubit multiple bit flip code that can completely protect the target qubit from all multiple bit flip errors using only CNOT gates. The proposed multiple bit flip codes can be easily extended to multiple phase flip codes by embedding Hadamard gate pairs in the root error section as in conventional single bit flip code. The multiple bit flip code and multiple phase flip code in this paper share the state vector error information by four auxiliary qubits. These four-qubit state vectors reflect the characteristic that all the multiple flip errors with Pauli X and Z corrections commonly include a specific root error. Using this feature, this paper shows that low-cost implementation is possible despite the QECC design for multiple-flip error correction by batch processing the detection and correction of Pauli X and Z root errors with only three CNOT gates. The five-qubit multiple bit flip code and multiple phase flip code proposed in this paper have 100% error correction rate and 50% error discrimination rate. All QECCs presented in this paper were verified using QCAD simulator.

• Korean Journal of Optics and Photonics
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• v.18 no.5
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• pp.323-332
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• 2007

The effect of the reflectivity of both facets and the phase of a phase tuning section on the self-pulsation (SP) characteristics of multisection complex-coupled (CC) DFB lasers is investigated in terms of yield. The lasers are composed of two CC DFB sections and a phase tuning section between them. As the coupling strength and the coupling ratio (CR) decrease, the effect of the reflected fields from both facets and the other DFB section on the mode characteristics of one DFB section increases, so that the yield decreases. As the facet reflectivity increases, the maximum yield and the range of the phase of a phase tuning section with yield more than 60% decrease independent of the coupling strength and CR. The yield characteristics of CR=0.2 are better than those of CR=0.1 with the same coupling strength due to the larger complex coupling effect. The case with ${\mid}{\kappa}L{\mid}=3$ and CR=0.2 shows best yield characteristics among the cases considered in this work.