• Composites Research
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• v.13 no.3
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• pp.9-20
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• 2000

Free vibration characteristics of a cantilevered laminated composite beam with multiple non-propagating transverse open cracks are investigated. In the present analysis a special ply-angle distribution referred to as asymmetric stiffness configuration inducing the elastic coupling between chord-wise bending and extension is considered. The multiple open cracks are modelled as equivalent rotational springs whose spring constants are calculated based on the fracture mechanics of composite material structures. Governing equations of a composite beam with open cracks are derived via Hamilton's Principle and Timoshenko beam theory encompassing transverse shear and rotary inertia effect is adopted. The effects of various parameters such as the ply angle, fiber volume fraction, crack numbers, crack positions and crack depthes on the free vibration characteristics of the beam with multiple cracks are highlighted. The numerical results show that the existence of the multiple cracks in an anisotropic composite beam affects the free vibration characteristics in a more complex fashion compared with the beam with a single crack.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.3
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• pp.48-57
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• 1999

안테나 단에서 직접 수신 신호의 디지털화가 이루어지고 그 해당 신호의 처리는 고속 디지털 신호처리기 내에서 소프트웨어로 수행되는 방식을 SWR(Software Radio)이라 한다. 그러나 현재의 기술 수준을 감안하여 보다 현실적인 SDR(Software Defined Radio) 정의가 필요하게 되었다. SDR이란 수신신호의 디지털화가 안테나 이하의 임의의 단(IF단)에서 이루어지는 무선으로 정의된다. 물론 A/D변환기등의 기술이 더욱 발전되면 궁극적으로는 SWR로 진화될 것이다. 그러면 SDR은 왜 필요한 것일까? 현재 사용중인 이동통신 단말기의 단점은 어느 한 표준 또는 방식에 종속되어 언제 어디서나 임의의 시스템에 접속되어 사용하기에는 많은 기술 종속적인 문제 및 제약을 내포하며, 사용방식에 따른 시스템의 유연성이 없고, 상용 서비스 도중에 발생되는 단말기 문제의 해결(recall service)이 어렵고, 많은 기술료를 지불해야 한다는 것이다. 부연하면 CDMA 셀룰라의 경우 퀄컴 등의 특정한 회사에 의해 기술이 폐쇠되어, 정보의 흐름이 자유스럽지 못할 뿐더러, 이로 인해 기술진화가 보다 빠르게 진행되지 못하고, 전세계적으로 많은 새로운 우수 제품의 출연에 제약이 가해진다는 것이다. 따라서 SDR(Software Defined Radion)을 도입, 하드웨어 및 소프트웨어를 개방형 구조(open architecture)로 개발한다면 정보의 흐름을 자유롭게 할 수 있고, 이로 인하여 세계적으로 다양한 신제품의 개발이 촉진되고 결과적으로 전세계 시장이 커지게 되는 일석이조의 효과를 얻을 수 있게 된다. 또한 이 같은 개방형 단말기 개발의 필요성은 최근 시장동향으로 볼 때, 기존의 단말기 회사 입장에서는 새로운 수익 모델이 필요한 시점이고, 또한 2002년경에 판매되는 단말기의 80%정도는 멀티모드타입 단말기일 것으로 예측되는 점, 그리고 금년말까지 100개 회사 이상이 SDR 포럼 멤버로 가입할 것으로 예측되는 점, 무선 인터넷 폭발적인 성장으로 복합 멀티미디어 단말기 시대가 다가오는 점 등으로 미루어 볼 때, 고객의 서비스 가치선택에 역점을 둔 기술을 중시해야 한다는 점에서 더욱 설득력을 지닌다. 따라서 이 같은 목적과 3세대 이동통신 및 인터넷 사용자의 증가, 반도체기술의 발전에 힘입어, 과거 군용 시스템에서 이용되던 SWR 기술을 상용시스템 특히 3세대 이동통신에 적용하려는 연구가 활발히 진행되고 있다. '96년 SDR 포럼이 결성되었는데, 목적은 휴대형 장치(hand-held devices), 기지국(base stations), 차량형 장치(mobile stations)를 포함하는 다중모드(multi-mode), 다중대역(multi-band) SDR을 위한 개방형 구조의 표준을 정하기 위함이다. 이 같이 public forum에 의한 표준(open architecture standard)이 정해지면 그 다음은 이를 어떻게 구현할 것인가가 문제가 될 것이다. 본고에서는 먼저 SDR 단말기 요구사항을 살펴보고, 이 요구사항들을 만족하는 SDR 단말기 구조, SDR 계층참조 모델, 그리고 기존의 단말기 구조와 SDR 계층참조 모델의 연관관계에 대해 살펴보고, 크게 두가지 종류의 단말기 즉 사용 SDR 단말기와 군용 SDR 단말기에 대해 살펴보고, 설계 절차 및 현재 시점에서 단말기 구현을 위해 해결해야 하는 기술적 과제를 살펴보고 결론을 언급한다.

• The Journal of the Acoustical Society of Korea
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• v.20 no.6
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• pp.34-39
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• 2001

An adaptive multi-rate (AMR) speech coder was adopted as a standard of W-CDMA by 3GPP and ETSI. The AMR coder is based on the CELP algorithm operating at rates ranging from 12.2 kbps down to 4.75 kbps, and it is a source controlled codec according to the channel error conditions and the traffic loading. In this paper, we implement the DSP S/W of the AMR coder using OakDSPCore. The implementation is based on the CSD17C00A chip developed by C&S Technology, and it is tested using test vectors, for the AMR speech codec, provided by ETSI for the bit exact implementation. The DSP B/W requires 20.6 MIPS for the encoder and 2.7 MIPS for the decoder. Memories required by the Am coder were 21.97 kwords, 6.64 kwords and 15.1 kwords for code, data sections and data ROM, respectively. Also, actual sound input/output test using microphone and speaker demonstrates its proper real-time operation without distortions or delays.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.4
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• pp.49-58
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• 2014

A low-swing differential near-ground signaling (NGS) transceiver for low-power high-speed mobile I/O interface is presented. The proposed transmitter adopts an on-chip regulated programmable-swing voltage-mode driver and a pre-driver with asymmetric rising/falling time. The proposed receiver utilizes a new multiple gain-path differential amplifier with feed-forward capacitors that boost high-frequency gain. Also, the receiver incorporates a new adaptive bias generator to compensate the input common-mode variation due to the variable output swing of the transmitter and to minimize the current mismatch of the receiver's input stage amplifier. The use of the new simple and effective impedance matching techniques applied in the transmitter and receiver results in good signal integrity and high power efficiency. The proposed transceiver designed in a 65-nm CMOS technology achieves a data rate of 13 Gbps/channel and 0.3 pJ/bit (= 0.3 mW/Gbps) high power efficiency over a 10 cm FR4 printed circuit board.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.2
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• pp.106-112
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• 2007

This paper proposes a hybrid architecture algorithm for fast computation of DCT and DFT via recursive factorization. Recursive factorization of DCT-II and DFT transform matrix leads to a similar architectural structure so that common architectural base may be used by simply adding a switching device. Linking between two transforms was derived based on matrix recursion formula. Hybrid acrchitectural design for DCT and DFT matrix decomposition were derived using the generation matrix and the trigonometric identities and relations. Data flow diagram for high-speed architecture of Cooley-Tukey type was drawn to accommodate DCT/DFT hybrid architecture. From this data flow diagram computational complexity is comparable to that of the fast DCT algorithms for moderate size of N. Further investigation is needed for multi-mode operation use of FFT architecture in other orthogonal transform computation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.12
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• pp.1343-1350
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• 2012

This paper presents a new method for designing a dual-band WIFI antenna using the third-order harmonic mode of a monopole antenna whose first-order mode operates at the low frequency band of WIFI. As analysing the current distribution of the third-order mode of this monopole antenna, the strongest point of electric field can be found. Then by attaching a stub at this point, the resonant frequency of the stub radiator can be adjusted from the third-order mode of the monopole antenna into the high frequency band of WIFI and the input impedance at this resonant frequency can be controlled with the width of the branch, without affecting the low frequency band of WIFI (the first-order mode of the monopole antenna). The compact dual-band antenna is designed at the size of an USB(universal serial bus) dongle and the bandwidth covers 600 MHz(2.3~3 GHz) at 2 GHz and 1 GHz(4.9~5.9 GHz) at 5 GHz under -10 dB which is satisfied with WLAN frequency. Efficiency of proposed antenna achieves over 50 % at WLAN frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.71-81
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• 2008

In this paper, we propose a novel Globally Asynchronous, Locally Dynamic System(GALDS) bus and demonstrate its performance. The proposed GALDS bus is the bidirectional multitasking bus with the segmented bus architecture supporting the concurrent operation of multi-masters and multi-slaves. By analyzing system tasks, the bus architecture chooses the optimal frequency for each If among multiples of bus frequency and thus we can reduce the overall power consumption. For efficient data communications between IPs operating in different frequencies, we designed an asynchronous and bidirectional FIFO based on an asynchronous wrapper with hand-shaking interface. In addition, since systems can be easily expandable by inserting bus segments, the proposed architecture has advantages in IP reusability and structural flexibility As a test example, a four-segment bus haying four masters and four slaves were designed by using Verilog HDL. We demonstrate multitasking operations with read/write data transfers by simulation when the ratios of operation frequency are 1:1, 1:2, 1:4 and 1:8. The data transfer mode is a 16 burst increment mode compatible with Advanced Microcontroller Bus Architecture(AMBA). The maximum operation latency of the proposed GALDS bus is 22 clock cycles for the bus write operation, and 44 clock cycles for read.

• The Journal of the Acoustical Society of Korea
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• v.30 no.6
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• pp.344-352
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• 2011

In this paper, the resonant characteristic of a Tonpilz transducer with a fixed tail mass has been studied by means of an equivalent circuit approach. An equivalent circuit has been designed to describe the characteristic of a Tonpilz transducer that has an additional resonance because of its fixed tail mass. The transmitting voltage response of the transducer calculated by the designed circuit has been compared with that by the FEA (finite element analysis) to confirm the validity of the circuit. This equivalent circuit approach produces identical results with the FEA, in which the variation of resonant frequencies and TVR has been clearly figured out in relation to the stiffness of the mounting fixture and the mass of the tail mass. The suggested equivalent circuit can be utilized to figure out the characteristics of the Tonpilz transducer more efficiently than FEA that requires much calculation time and revision of the models in accordance with the variation of design variables.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.85-94
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• 2003

The asynchronous design methods proved to have the higher performance in power consumption and execution speed than synchronous ones because it just needs to activate the required module without feeding clock in the system. Despite the advantage of CISC machine providing the variable addressing modes and instructions, its execution scheme is hardly suited for a synchronous Pipeline architecture and incurs a lot of overhead. This paper proposes a novel asynchronous pipeline architecture, A80sl, whose instruction set is fully compatible with that of Intel 80C51, an embedded micro controller. We classify the instructions into the group keeping the same execution scheme for the asynchronous pipeline and optimize it eliminating the bubble stage that comes from the overhead of the multi-cycle execution. The new methodologies for branch and various instruction lengths are suggested to minimize the number of states required for instructions execution and to increase its parallelism. The proposed A80C51 architecture is synthesized with 0.35${\mu}{\textrm}{m}$ CMOS standard cell library. The simulation results show higher speed than that of Intel 80C51 with 36 MHz and other asynchronous counterparts by 24 times.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.12
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• pp.66-71
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• 2014

This paper presents an analog front-end integrated circuit (IC) for medical ultrasound imaging systems using standard $0.18-{\mu}m$ CMOS process. The proposed front-end circuit includes the transmit part which consists of 15-V high-voltage pulser operating at 2.6 MHz, and the receive part which consists of switch and a low-power low-noise preamplifier. Depending on the operation mode, the output driver in the transmit pulser can be reconfigured as the switch in the receive path and thus the area of the overall front-end IC is reduced by over 70% in comparison to previous work. The designed single-channel front-end prototype consumes less than $0.045mm^2$ of core area and can be utilized as a key building block in highly-integrated multi-array ultrasound medical imaging systems.