• Proceedings of the Korean Society of Marine Engineers Conference
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• 2006.06a
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• pp.301-302
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• 2006

초고주파 전력 증폭기의 바이어스 전압을 조절하여 온도 변화에 따른 드레인(Drain) 전류의 변화를 억제하기 위한 저가의 능동 바이어스 모듈을 개발한다. 능동 바이어스 모듈을 5 W급 초고주파 전력증폭기에 적용하였을 경우, $0{\sim}60^{\circ}C$까지의 온도변화에 대하여 소모전류 변화량은 0.1 A 이하로 되어야 한다. 본 기술 개발 대상인 능동 바이어스 모듈의 성능 시험을 위한 대상 전력증폭기는 $2.11{\sim}2.17GHz$ 주파수 대역에서 32 dB 이상의 이득과 ${\pm}0.1\;dB$ 이하의 이득 평탄도, -15 dB 이하의 입.출력 반사손실을 가진다.

• Journal of Navigation and Port Research
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• v.28 no.3
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• pp.213-219
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• 2004

In this paper, a LNA(Low Noise Amplifier) has been developed, which is operating at L-band i.e., 1452∼1492 MHz for satellite DAB(Digital Audio Brcadcasting) receiver. The LNA is designed to improve input and output reflection coefficient and VSWR(Voltage Standing Wave Ratio) by balanced amplifier. The LNA consists of low noise amplification stage and gain amplification stage, which make a using of GaAs FET ATF-10136 and VNA-25 respectively, and is fabricated by hybrid method. To supply most suitable voltage and current, active bias circuit is designed Active biasing offers the advantage that variations in $V_P$ and $I_{DSS}$ will not necessitate a change in either the source or drain resistor value for a given bias condition. The active bias network automatically sets $V_{gs}$ for the desired drain voltage and drain current. The LNA is fabricated on FR-4 substrate with RF circuit and bias circuit, and integrated in aluminum housing. As a reults, the characteristics of the LNA implemented more than 32 dB in gain. 0.2 dB in gain flatness. lower than 0.95 dB in noise figure, 1.28 and 1.43 each input and output VSWR, and -13 dBm in $P_{1dB}$.

• Journal of Navigation and Port Research
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• v.27 no.1
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• pp.81-86
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• 2003

In the paper, the power amplifier using active biasing for LDMOS MRF-21060 is designed and fabricated. Driving amplifier using AH1 and parallel power amplifier AH11 is made to drive the LDMOS MRF 21060 power amplifier. The variation of current consumption in the fabricated 5 Watt power amplifier has an excellent characteristics of less than 0.1A, whereas passive biasing circuit dissipate more than 0.5A. The implemented power amplifier has the gain over 12 dB, the gain flatness of less than $\pm$0.09dB and input and output return loss of less than -19dB over the frequency range 2.11~2.17GHz. The DC operation point of this power amplifier at temperature variation from $0^{\circ}C$ to $60^{\circ}C$ is fixed by active circuit.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.6
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• pp.514-520
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• 2002

In this paper, the study of a design and fabrication of the receiver MMIC mixer for L-band application is described. The mixer is composed of active LO and RF balun to integrate on a chip and applied a newly proposed bias circuit to compensate the process variations of active devices. The conversion gain of the mixer is -14 dB, IIP3 is approximately 4 dBm and port-to-port isolation is over 25 dB. The newly proposed bias circuit is composed of a few FETs and resistors, and can compensate the variation of the threshold voltage by the process variations, temperature changes and etc. The designed chip size is $1.4\;mm{\times}1.4\;mm$.

• Journal of Advanced Marine Engineering and Technology
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• v.32 no.8
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• pp.1263-1268
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• 2008

In this paper, the low noise power amplifier for GaAs FET ATF-10136 is designed and fabricated with active bias circuit and self bias circuit. To supply most suitable voltage and current, active bias circuit is designed. Active biasing offers the advantage that variations in the pinch-off voltage($V_p$) and saturated drain current($I_{DSS}$) will not necessitate a change in either the source or drain resistor value for a given bias condition. The active bias network automatically sets a gate-source voltage($V_{gs}$) for the desired drain voltage and drain current. Using resistive decoupling circuits, a signal at low frequency is dissipated by a resistor. This design method increases the stability of the LNA, suitable for input stage matching and gate source bias. The LNA is fabricated on FR-4 substrate with active and self bias circuit, and integrated in aluminum housing. As a results, the characteristics of the active and self bias circuit LNA implemented more than 13 dB and 14 dB in gain, lower than 1 dB and 1.1 dB in noise figure, 1.7 and 1.8 input VSWR at normalized frequency $1.4{\sim}1.6$, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.11 s.102
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• pp.1114-1122
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• 2005

In this paper, the study of a design, fabrication and measurement of the receiver MMIC LNA, mixer for S-band application is described. The LNA is designed by 2-stage common source. The mixer is composed of active LO and RF balun to integrate on a chip and applied a newly proposed bias circuit to compensate the process variations of active devices. The LNA has 15.51 dB-gain and 1.02dB-Noise Figure at 2.1 GHz. The conversion gain of the mixer is -12 dB, IIP3 is approximately 4.25 dBm and port-to-port isolation is over 25 dB. The newly proposed bias circuit is composed of a few FETs and resistors, and can compensate the variation of the threshold voltage by the process variations, temperature changes and etc. The designed chip size is $1.2[mm]\times1.4[mm]$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.8 no.1
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• pp.94-99
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• 1997

There are several factors that have influence on the phase noise of an oscillator. But one of the major factors is the flicker noise of a transistor, since the phase noise of an oscillator is generated by mixing the carrier with the low frequency noise near the DC having the characteristic of 1/f. In this paper, we have presented a method on reducing the phase noise of an oscillator by using a low-frequency feedback circuit based on an active bias circuit, and have fabricated a DRO for a DBS receiver. Measurement results show that the phase noise is -92 dBc/Hz at the 10 KHz offset frequency, and from these results we have found out that the reduction method is very effective.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.3
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• pp.569-577
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• 1999

A wideband RF receiver for satellite mobile communications system was fabricated and evaluated of performance in low noise amplifier and high gain amplifier. The low noise amplifier used to the resistive decoupling and self-bias circuits. The low noise amplifier is fabricated with both the RF circuits and the self-bias circuits. Using a INA-03184, the high gain amplifier consists of matched amplifier type. The active bias circuitry can be used to provide temperature stability without requiring the large voltage drop or relatively high-dissipated power needed with a bias stabilized resistor. The bandpass filter was used to reduce a spurious level. As a result, the characteristics of the receiver implemented here show more than 55 dB in gain, 50.83 dBc in a spurious level and less than 1.8 : 1 in input and output voltage standing wave ratio(VSWR), especially the carrier to noise ratio is a 43.15 dB/Hz at a 1 KHz from 1537.5 MHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.6
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• pp.560-566
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• 2004

In this paper, active frequency doubler with broadband characteristics from 6 ㎓ to 12 ㎓ was designed and fabricated using PHEMT. The designed frequency multiplier has a bias point near pinch-off and a proposed series RC circuit between bias line and input matching network far the improvement of stability. With 0 ㏈m input power, second harmonic of 1.7 ㏈m at 12 ㎓ -27.5 ㏈c suppression of 6 ㎓ fundamental, -18 ㏈c suppression of 18 ㎓ 3rd harmonic, and the 3 ㏈ output bandwidth of 1,8 ㎓ have been measured.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.168-170
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• 2019

본 논문은 효과적인 능동 풀-다운 기능을 위한 새로운 구조의 펄스 파워 모듈레이터를 제안한다. 제안된 능동 풀-다운 방식은 별도의 풀-다운 저항을 사용하지 않고, 펄스 방전 패스에 추가된 다이오드의 역회복 특성을 이용하여 풀-다운 기능을 수행한다. 본 논문에서 사용된 풀-다운 다이오드는 펄스 출력 시에는 정방향 바이어스 상태를 유지하다가, 펄스 출력이 제거되면 비교적 긴 역회복 구간동안 부하의 커패시턴스 성분에 남아있는 에너지가 방전될 수 있는 전류 패스를 제공한다. 이에 따라 제안된 구조의 펄스 모듈레이터는 기존에 제안된 풀-다운 회로에서 발생하는 발열 손실 또는 별도의 복잡한 제어회로와 같은 복잡한 구조의 문제를 보완하고 빠른 펄스 하강시간을 달성할 수 있다. 본 논문에서는 시뮬레이션을 통해 기존에 제안되었던 풀-다운 저항 방식과 풀-다운 스위치 방식, 제안하는 방식을 비교하여 제안된 구조의 성능과 우수성을 분석하였다.