• The Journal of Korean Association of Computer Education
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• v.11 no.1
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• pp.23-32
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• 2008

In this paper, we have investigated the education effect of a web-based virtual laboratory for digital logic circuits which consists of multimedia contents about the usages of equipments for logic circuit experiments and the experimental logic circuits. In case of the engineering experiment of the lower grades in universities, preunderstanding about the usages of experimental equipments and the experimental circuits is necessary for the learners to conduct the experiments well. But it is impossible for the learners to have access to the real experimental equipments earlier due to the lack of equipments and the difficulty in management of the equipments. We have implemented the digital logic circuit virtual laboratory which provides the same experimental environment as a real experimental lab, and the learner can conduct the same experiments as the real ones before the real laboratory class. The learners using the laboratory have reduced the experiment completion time by the average of about 8.2% during a term, compared with the learners not using the lab.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.5
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• pp.682-687
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• 2022

In this paper, the research results on monolithic three-dimensional integrated-circuit (M3DICs) stacked with tunneling field effect transistors (TFETs) are introduced. Unlike metal-oxide-semiconductor field-effect transistors (MOSFETs), TFETs are designed differently from the layout of symmetrical MOSFETs because the source and drain of TFET are asymmetrical. Various monolithic 3D inverter (M3D-INV) structures and layouts are possible due to the asymmetric structure, and among them, a simple inverter structure with the minimum metal layer is proposed. Using the proposed M3D-INV, this M3D logic gates such as NAND and NOR gates by sequentially stacking TFETs are proposed, respectively. The simulation results of voltage transfer characteristics of the proposed M3D logic gates are investigated using mixed-mode simulator of technology computer aided design (TCAD), and the operation of each logic circuit is verified. The cell area for each M3D logic gate is reduced by about 50% compared to one for the two-dimensional planar logic gates.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.17-26
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• 2016

This work proposes a 12b 60MS/s 0.18um CMOS Flash-SAR ADC for various systems such as wireless communications and portable video processing systems. The proposed Flash-SAR ADC alleviates the weakness of a conventional SAR ADC that the operation speed proportionally increases with a resolution by deciding upper 4bits first with a high-speed flash ADC before deciding lower 9bits with a low-power SAR ADC. The proposed ADC removes a sampling-time mismatch by using the C-R DAC in the SAR ADC as the combined sampling network instead of a T/H circuit which restricts a high speed operation. An interpolation technique implemented in the flash ADC halves the required number of pre-amplifiers, while a switched-bias power reduction scheme minimizes the power consumption of the flash ADC during the SAR operation. The TSPC based D-flip flop in the SAR logic for high-speed operation reduces the propagation delay by 55% and the required number of transistors by half compared to the conventional static D-flip flop. The prototype ADC in a 0.18um CMOS demonstrates a measured DNL and INL within 1.33LSB and 1.90LSB, with a maximum SNDR and SFDR of 58.27dB and 69.29dB at 60MS/s, respectively. The ADC occupies an active die area of $0.54mm^2$ and consumes 5.4mW at a 1.8V supply.

• Journal of KIISE:Software and Applications
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• v.36 no.2
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• pp.153-160
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• 2009

As size of ontology has been increased more and more, the descriptions in the ontologies become more complicated, Therefore finding and modifying unsatisfiable concepts is hard work in ontology construction process, Minerva is an ontology reasoner which detects unsatisfiable concepts automatically and infers subsumption relation between concepts in ontology, Most description logic based ontology reasoners (including Minerva) work using tableaux algorithm, Because tableaux algorithm is very costly, ontology reasoners need various optimization methods, In this paper, we propose optimizing methods to reduce execution time of tableaux algorithm based ontology reasoner. Proposed methods were applied to Minerva which was developed as preceding study result. In consequence the new version Minerva shows high performance.

• The KIPS Transactions:PartA
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• v.14A no.3 s.107
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• pp.147-150
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• 2007

This paper describes a new low-swing inverter for low power consumption. To reduce a power consumption, an output voltage swing is in the range from 0 to VDD-2VTH. This can be done by the inverter structure that allow a full swing or a swing on its input terminal without leakage current. Using this low-swing voltage technology, we proposed a low-power 16$\times$16 bit parallel multiplier. The proposed circuits are designed with Samsung 0.35$\mu$m standard CMOS process at a 3.3V supply voltage. The validity and effectiveness are verified through the HSPICE simulation.. Compared to the previous works, this circuit can reduce the power consumption rate of 17.3% and the power-delay product of 16.5%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.1
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• pp.59-64
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• 2008

In this paper, we developed an virtual lecture to study digital logic circuits. The contents is intended fer the students without or with little knowledge about electrics or electronics. For the beginners, the lecture contains the basic electronics and basic circuit theory as well as the degital logic circuits to be more practical lecture. And we developed the virtual circuit lab which uses real-like devices, circuits and interactive objects for the students to experience practical digital circuits. With the features described above, this contents would be useful for the beginners who want to studying digital logic circuits.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2007.11a
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• pp.308-311
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• 2007

대부분의 센서 네트워크에서 센서 노드들은 열린 환경에서 독립적으로 동작하므로 보안 공격에 취약하다. 허위 보고서 삽입 공격에서 공격자는 허위 경보를 발생시키거나 혹은 네트워크 내 에너지의 고갈을 목적으로 포획된 노드들을 통해 허위 보고서를 네트워크에 삽입한다. 이러한 허위 보고서를 조기에 검출, 제거하기 위해 많은 여과 기법들이 제안되었다. 가환 암호 기반 여과 기법에서 각각의 중간 노드는 확률에 기반 하여 보고서 인증을 수행한다. 따라서 허위 보고서가 여과되지 않거나 정상 보고서가 여러 번 인증 받을 가능성이 있다. 또한 네트워크의 상태 변화에 적응하기 어렵다. 본 논문은 퍼지 논리를 이용한 무선 센서 네트워크에서의 임계값 기반 여과 기법을 제안한다.

• The Transactions of the Korean Institute of Power Electronics
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• v.7 no.3
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• pp.215-223
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• 2002

This paper investigates the adaptive control of a fuzzy logic based speed and flux controller fur a vector controlled induction motor drive. A model reference adaptive scheme is proposed in which the adaptation mechanism is executed by fuzzy logic based on the error and change of error measured between the motor speed and output of a reference model. The control performance of the model reference adaptive control(MRAC) fuzzy controller is evaluated by simulation for various operating conditions. The validity of the Proposed MRAC fuzzy controller is confirmed by performance results for induction motor drive system.

• Proceedings of the KIPE Conference
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• 2004.07a
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• pp.411-414
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• 2004

본 연구에서는 RPP(Randomized Pulse Position PWM)의 특징과 RSF(Random Switching Frequency PWM)의 특징을 모두 갖는 하이브리드 RPWM (Random PWM)기법을 제안하였다. 제안된 방법은 PRBS(Pseudo-Random Binary Sequence)로 동작하는 시프트 레지스터의 lead-lag 랜덤 비트를 사용한다는 점에서 종전의 방법과 동일하나, 이와 논리적인 비교를 위해 랜덤 주파수의 삼각파를 이용한다는 점에서 종전의 방법과 다르다. 본 연구의 타당성을 확인하기 위하여 인버터 기반의 3상 유도모터 구동시스템에 제안된 방법을 적용하였다. 그 결과 종전의 방법에 비하여 인버터 구동 유도모터의 전압 및 전류의 고조파 스펙트럼의 광 대역화에 탁월한 효과가 있음을 입증할 수 있었다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.3B
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• pp.347-354
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• 2001

IEEE 1394 버스는 데이터 패킷 전송시 반이중(half duplex)으로, 0과 1의 두 상태를 이용하여 전송한다. 그러나 버스 자동 구성 및 중재 기간에서 양방향으로 버스 중재 선 상태(arbitrtation line state) 신호를 주고받으며, 이는 Z, 0. 1의 세 논리 상태를 가지고 있다. IEEE 1394 버스를 채택한 노드는 시스템에 연결시 자동으로 네트웍을 트리 구조로 구성하고, 6 비트 물리 ID를 할당하며, 이는 버스 리셋, 트리 식별, 자기 식별의 세과정을 통해 구성된다. 또 전송할 데이터가 있는 경우 노드는 버스의 사용권을 얻기 위한 버스 중재(arbitration) 후 전송을 시작한다. 이러한 시스템 자동 구성을 위한 과정들과 버스 중재 과정에서 양방향으로 아날로그 0, 1, Z의 중재 선 상태 신호를 주고받게 된다. 본 논문에서는 기존 IEEE 1394를 채택한 노드들과 화환되며 중재 선 상태를 0과 1의 논리 상태만을 사용하여 버스 자동 구성 및 버스 중재를 디지털 회로로 구성할 수 있는 중재 선 상태 디코딩 알고리즘을 제안하였고, VHDL을 이용하여 전체 시스템의 동작을 시뮬레이션하였다.