• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.449-449
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• 2013

최근 반도체 소자의 집적회로는 점점 복잡해지고 있는 반면, 소자의 크기는 작아지고 있으며 그로 인해 패드의 크기가 작아지고 패드사이의 간격 또한 협소해지고 있다. 따라서 웨이퍼 단계에서 제조된 집적회로의 불량여부를 판단하기위한 검사 장비인 프로브카드(Probe Card)의 높은 집적도가 요구되고 있다. 하지만 기존의 MEMS 공법으로 제작되는 프로브 빔은 복잡한 제조 공정과 높은 생산비용, 낮은 집적도의 문제점을 가지고 있다. 본 연구에서는 이러한 문제점을 해결하기 위하여 간단한 제조 공정과 낮은 생산비용, 높은 집적도를 가지는 프로브 빔을 개발하기 위하여 절연절단 방식으로 BeCu (Beryllium-Copper) 프로브 빔을 제작하였다. 낮은 소비 전력으로 우수한 프로브 빔 어레이를 제작하기 위해서 가장 고려해야할 대상은 프로브 빔의 재료와 구조(형상)이다. 절연전단 방식으로 프로브 빔을 형성할 때 요구되는 Fusing current는 프로브 빔의 구조(형상)에 크게 영향을 받는다. 낮은 Fusing current는 소비 전력을 줄여주고, 절연절단으로 형성되는 프로브 빔의 단면(끝)을 날카롭게 하여 프로브 빔과 집적회로의 패드 간의 접촉 저항을 감소시킨다. 프로브 빔의 제작은 BeCu 박판을 빔 형태로 식각하여 제작하였으며, 실리콘 비아 홀(Via hole) 구조의 기판위에 정렬하여 soldering 공정을 통해 실리콘 기판과 BeCu 박판을 접합시켰다. 접합된 프로브 빔의 끝부분을 들어 올린 상태로 전류를 인가하여 stress free 상태로 만들어 내부 응력을 제거하였으며, BeCu 박판에 fusing current를 인가하여 BeCu 박판 프레임으로부터 제거를 하였다. 제작된 프로브 빔의 길이는 1.7 mm, 폭은 $50{\mu}m$, 두께는 $15{\mu}m$, 절단부의 단면적은 1$50{\mu}m^2$로 제작되었다. 그리고 프로브 빔의 절단부의 길이는 $50{\mu}m$ 부터 $90{\mu}m$까지 $10{\mu}m$ 증가시켜 제작되었다. 이후에 절연절단 공정에 요구되는 Fusing current를 측정하였고, 절연절단 후의 절단면의 형상을 SEM (Scanning Electron Microscope)장비를 통하여 확인하였다. 절단부의 길이가 $50{\mu}m$일 때 5.98A의 fusing current를 얻었으며, 절연절단 후 절단부 상태 또한 가장 우수했다. 본 연구에서 제안된 프로브 빔 제작 방법은 프로브카드 및 테스트 소켓(Test socket) 생산에 응용이 가능하리라 기대한다.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.1
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• pp.1-6
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• 2004

The requirements for harsh environment electronic controllers in automotive applications have been steadily becoming more and more stringent. Electronic substrate technologists have been responding to this challenge effectively in an effort to meet the performance, reliability and cost requirements. An effect of the plasma cleaning at the ECM(Engine Control Module) alumina substrate and the intermetallic compound layer between Sn-37wt%Pb solder and pad joints after reflow soldering has been studied. Organic residual carbon layer was removed by the substrate plasma cleaning. So the interfacial adhesive strength was enhanced. As a result of AFM measurement, conductor pad roughness were increased from 304 nm to 330 nm. $Cu_6/Sn_5$ formed during initial reflow process at the interface between TiWN/Cu pad and solder grew by the succeeding reflow process, so the grains became coarse. A cellular-shaped $Ag_3Sn$ was observed at the interface between Ag-Pd conductor pad and solder. The diameters of the $Ag_3Sn$ grains ranged from about 0.1∼0.6 $\mu\textrm{m}$. And a needle-shaped was also observed at the inside of the solder.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.3 s.40
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• pp.39-45
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• 2006

This study was investigated the thermal properties of underfill with various epoxy resins using thermal analysis methods such as differential scanning calorimetry (DSC), thermo gravimetry analysis (TGA), dynamic mechanical analysis (DMA) and thermo-mechanical analysis (TMA). And, the adhesion strength of the underfills/FR-4 substrate was evaluated. The glass transition temperature (Tg) of underfill which was composed the cycolaliphatic epoxy resin was lower than that of underfill which was not composed the cycolaliphatic epoxy resin. The thermal degradation of underfill was composed of two processes, which involved chemical reactions between the degrading polymer and oxygen from the air atmosphere. The coefficient of thermal expansion (CTE) of underfill which was composed the cycolaliphatic epoxy resin was higher than that of underfill which was not composed the cycolaliphatic epoxy resin. The excessive curing temperatures caused a weak boundary layer of epoxy resin, which resulted in a deterioration of mechanical properties in the epoxy resin and thus led to poor adhesion property between the underfill/FR-4 substrate.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.10
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• pp.752-757
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• 2018

This study presents the performance evaluation results of a 77-GHz waveguide slot array antenna that was fabricated by attaching a patterned printed circuit board(PCB) on a metal block. The 77-GHz waveguide was divided into a top plate and a bottom structure. The top plate was fabricated using a patterned PCB that can implement a fine slot at low cost. The top cover was then bonded to the bottom metal structure with a waveguide trough using anisotropic conductive film. For evaluating the antenna performance, a $1{\times}16$ slot array antenna was fabricated using our proposed method and the gain and pattern were measured and compared with the simulation results. Though the measurement results demonstrate a reduction in gain of around 2.3~3.5 dB compared to the simulation results assuming ideal bonding conditions, the pattern hardly changed and the slot antenna with a gain of approximately 17 dBi at 77 GHz can be easily manufactured at a low cost using the proposed method.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.42 no.9
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• pp.789-794
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• 2014

The FPGA is used to the high speed digital satellite communication on the Digital Signal Process Unit of the next generation GEO communication satellite. The high capacity FPGA has the high power dissipation and it is difficult to satisfy the derating requirement of temperature. This matter is the major factor to degrade the equipment life and reliability. The thermal control at the equipment level has been worked through thermal conduction in the space environment. The FPGA of CCGA or BGA package type was mounted on printed circuit board, but the PCB has low efficient to the thermal control. For the FPGA heat dissipation, the heat sink was applied between part lid and housing of equipment and the performance of heat sink was confirmed via thermal vacuum test under the condition of space qualification level. The FPGA of high power dissipation has been difficult to apply for space application, but FPGA with heat sink could be used to space application with the derating temperature margin.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.1
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• pp.7-13
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• 1998

The VLSI devices of submicron level trend to have a lowering of reliability because of hot carriers by two dimensional influences which are caused by short channel effects and which are not generated in a long channel devices. In order to minimize the two dimensional influences, much research has been made into various types of source/drain structures. MOS typed tunnel transistor with Schottky barrier junctions at source/drain, which has the advantages in fabrication process, downsizing and response speed, has been proposed. The experimental device was fabricated with p type silicon, and manifested the transistor action, showing the unsaturated output characteristics and the high transconductance comparing with that in field effect mode. The results of trial indicate for better performance as follows; high doped channel layer to lower the driving voltage, high resistivity substrate to reduce the leakage current from the substrate to drain.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.111-118
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• 2018

In order to develop a local stiffness-variant stretchable substrate with the soft PDMS/hard PDMS/FPCB configuration consisting of two stiffness-different polydimethylsiloxane (PDMS) parts and flexible printed circuit board, a FPCB was bonded to PDMS using the acrylic-silicone double-sided tape and the interfacial adhesion of the PDMS/FPCB was evaluated. The pull strength of the FPCB, which was bonded to the fully cured PDMS using the silicone adhesive of the double-sided tape, was 259 kPa and the delamination during the pull test occurred at the interface between the PDMS and the silicone adhesive. On the contrary, the bonding process, for which the FPCB was bonded using the silicone adhesive to the PDMS partially cured for 15~20 minutes at $60^{\circ}C$ and then the PDMS was fully cured for 12 hours at $60^{\circ}C$, exhibited the remarkably enhanced pull strength of 1,007~1,094 kPa. With the above mentioned bonding process, the delamination during the pull test was observed at the interface between the FPCB and the acrylic adhesive of the acrylic-silicone double sided tape.

• Journal of Adhesion and Interface
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• v.24 no.3
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• pp.86-94
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• 2023

To fabricate all-solution-processed flexible Organic Light-Emitting Diodes (OLEDs), we demonstrated a bonding technology using a polyethyleneimine (PEI) as an adhesion layer between the two substrates. As the adhesion layer requires not only a high adhesion strength, but also a high current density, we have tried to find out the optimum condition which meets the two requirements at the same time by changing experimental factors such as PEI concentration, thickness of the layer and by mixing some additives into the PEI. The adhesion strength and the electrical current density were investigated by tensile tests and electron only device (EOD) experiments, respectively. The results showed that at higher PEI concentration the adhesion strength showed higher value, but the electrical current through the PEI layer decreased rapidly due to the increased PEI layer thickness. We added Sorbitol and PolyEthyleneGlycohol (PEG) into the 0.1 wt% PEI solution to enhance the adhesion and electrical properties. With the addition of the 0.5 wt% PEG into the 0.1 wt% PEI solution, the device showed an electrical current density of 900 mA/cm² and a good adhesion characteristic also. These data demonstrated the possibility of fabricating all-solution-processed OLEDs using two-substrate bonding technology with the PEI layer as an adhesion layer.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.4
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• pp.39-46
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• 2017

This paper presents the fabrication of ceramic insulation layer on metallic heat spreading substrate, i.e. an insulated metal substrate, for planar type heater. Aluminum alloy substrate is preferred as a heat spreading panel due to its high thermal conductivity, machinability and the light weight for the planar type heater which is used at the thermal treatment process of semiconductor device and display component manufacturing. An insulating layer made of ceramic dielectric film that is stable at high temperature has to be coated on the metallic substrate to form a heating element circuit. Two technical issues are raised at the forming of ceramic insulation layer on the metallic substrate; one is delamination and crack between metal and ceramic interface due to their large differences in thermal expansion coefficient, and the other is electrical breakdown due to intrinsic weakness in dielectric or structural defects. In this work, to overcome those problem, selected metal oxide buffer layers were introduced between metal and ceramic layer for mechanical matching, enhancing the adhesion strength, and multi-coating method was applied to improve the film quality and the dielectric breakdown property.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.3
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• pp.63-67
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• 2016

In this paper, we present an indirect method of elastic modulus measurement for various lamination layers formed on polymer-based compliant substrates. Although the elastic modulus of every component is crucial for mechanically reliable microelectronic devices, it is difficult to accurately measure the film properties because the lamination layers are hardly detached from the substrate. In order to resolve the problem, 3-point bending test is conducted with a film-substrate specimen and area transformation rule is applied to the cross-sectional area of the film region. With known substrate modulus, a modulus ratio between the film and the substrate is calculated using bending stiffness of the multilayered specimen obtained from the 3-point bending test. This method is verified using electroplated copper specimens with two types of film-substrate structure; double-sided film and single sided film. Also, common dielectric layers, prepreg (PPG) and dry film solder resist (DF SR), are measured with the double-sided specimen type. The results of copper (110.3 GPa), PPG (22.3 GPa), DF SR (5.0 GPa) were measured with high precision.