• Proceedings of the KIEE Conference
• /
• 2009.07a
• /
• pp.1568_1569
• /
• 2009

RFID 수동 태그의 동작 원리를 이용하여 USN/WBAN 센서 노드 시스템에 적용 가능한 웨이크 업 회로를 설계하였다. 웨이크 업회로 구성은 크게 전압 체배기, 복조기, 상태기계로 구성되었다. 상태 기계에 동작 가능한 전압을 공급하기 위해 전압 체배기는 문턱 전압 제거 방식을 적용한 구조를 사용하였고, 복조기 회로로는 AM 복조기로 구조가 간단한 포락선 검파기 방식을 사용하였다. 전압 체배기에 높은 전압이 인가될 경우 회로가 파괴되는 것을 막기 위해 제한 회로를 구성하여 최대 전압을 2.1V로 제한하였다. 또한 복조기에서는 안정적인 데이터 복조를 위해 비교기의 기준전압을 입력신호의 평균값을 사용한 슈미트 트리거 비교기를 사용하여 안정적으로 데이터를 추출하였다. 삼성 0.18um CMOS 공정을 이용하여 설계하였고, 측정 결과 전압 체배기의 체배 전압은 2.07~1.76V까지 체배 되는 것을 확인하였고, 복조기의 데이터 복조 역시 약 4M의 거리까지 데이터를 복조함을 확인하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.11
• /
• pp.41-47
• /
• 2011

A novel digital instrumentation amplifier(DIA) converting universal signal inputs into 5V voltage-output for industry standard sensor signal processing was designed. The circuit consists of a commercial instrumentation amplifier, seven analog switches, two voltage references of 1.0V and -10.0V, and four resistors. The converting principle is the circuit reconstruction by switches for resistor values and reference voltages according to input signals. The simulation result shows that the DIA has a good output voltage characteristics of 0~5V for the input voltage of 0V~5V, 1V~5V, -10V~+10V, and 4mA~20mA. The nonlinearity error was less than 0.1% for the four type signal inputs.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.11
• /
• pp.16-23
• /
• 2009

A 12b 10MS/s pipelined ADC with low DC gain amplifiers is presented. The pipelined ADC using a reference scaling technique is proposed to compensate the gain error in MDACs due to a low DC gain amplifier. To minimize the performance degradation of the ADC due to amplifier offset, the proposed offset trimming circuit is employed m the first-stage MDAC amplifier. Additional reset switches are used in all MDACs to reduce the memory effect caused by the low DC gain amplifier. The measured differential and integral non-linearities of the prototype ADC with 45dB DC gain amplifiers are less than 0.7LSB and 3.1LSB, respectively. The prototype ADC is fabricated in a $0.35{\mu}m$ CMOS process and achieves 62dB SNDR and 72dB SFDR with 2.4V supply and 10MHz sampling frequency while consuming 19mW power.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.9
• /
• pp.49-56
• /
• 1998

In this paper, a design of bias circuit in temperature independent voltage detect circuit is proposed. In order to realize this intention, we are used the differences in temperature coefficient of thermal voltage, resistor and transistor forward voltage(V$\sub$BE/) which is consisted in comparator. That is, It is realized by compensating the difference of temperature coefficient due to using components with each different temperature coefficient. As well, reference voltage of the circuit is accomplished by the difference of transistor forward voltage($\Delta$V$\sub$BE/) in comparator. In using reference voltage, resistor and V$\sub$BE/ Multiplier, we can design detect voltage of the circuit. In order to test operation of proposing circuit, we manufactured IC. Then, we measured operating characteristics and capability of the circuit by using HP4145B and temperature chamber. The result, we could obtain the good variation of temperature from -0.01 %/$^{\circ}C$ to -0.025 %/$^{\circ}C$.

• Proceedings of the KIEE Conference
• /
• 2003.07a
• /
• pp.27-29
• /
• 2003

최근, 배전계통의 고압 배전선로의 전압강하가 5%를 초과하는 장거리 선로에 대한 효율적인 전압관리가 미흡한 상태이며, 배전선로의 전압을 제어하기 설치하는 선로 전압조정장치(Step Voltage Regulator : SVR)의 잦은 고장 및 설치공간 과다점유로 전압조정장치의 설치 사용실적이 미진하고, 동 기기의 운용 및 설치기준에 정립이 시급한 실정이다. 따라서 전압강하 5% 초과 지역에 대한 효율적인 전압관리 개선방안을 강구하기 위하여, 현재 배전사업소에 도입, 설치되고 있는 전압조정 장치(SVR)의 운용기준 제정은 물론, 적정용량 및 최적 위치선정에 대한 방안을 제시하는 연구가 필요하다.

• Proceedings of the KIEE Conference
• /
• 2007.07a
• /
• pp.459-460
• /
• 2007

전압은 무효전력과 밀접한 연관성을 가지기 때문에 전체 계통의 전압 운영은 통일된 기준이 아니라 지역별로 수립되어야 한다. 이러한 사실을 바탕으로 본 논문에서는 우리나라 계통의 상황을 고려하여 기 운전된 실적 데이터를 지역별로 구분하여 분석하고 그 결과를 이용하여 지역별 전압 운영 기준을 검토한다.

• Proceedings of the KIEE Conference
• /
• 2004.05b
• /
• pp.207-209
• /
• 2004

저압간선의 굵기산정시 일반적으로 간이 계산식이 사용되고 있으나 이는 교류 임피던스를 적용한 정식과는 허용 전압강하를 기준으로한 포설거리에서 차이가 있으므로 저압간선의 설계시 보다 정확한 계산을 위해 교류 임피던스를 기준으로한 정식을 사용하여 계산이 이루어져야 한다. 따라서, 본 논문에서는 정식과 간이식에 따른 계산결과와 실측을 통한 전압강하를 비교하여 정확한 전압강하 계산법을 검토하여 보았다.

• Journal of Korea Society of Industrial Information Systems
• /
• v.20 no.6
• /
• pp.29-36
• /
• 2015

This paper presents an LED backlight driver IC consisting of three linear current regulators and an output-voltage regulation loop with a self-adjustable reference voltage. In the proposed LED driver, the output voltage is controlled by dual feedback loops. The first loop senses and controls the output voltage, and the second loop senses the voltage drop of the linear current regulator and adjusts the reference voltage. With these feedback loops, the voltage drop of the linear current regulator is maintained at a minimum value, at which the driver efficiency is maximized. The output of the driver is a three-channel LED setup with four LEDs in each channel. The luminance is adjusted by the PWM dimming signal. The proposed driver is designed by a $0.35-{\mu}m$ 60-V high-voltage process, resulting in an experimental maximum efficiency of approximately 85%.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.10
• /
• pp.69-75
• /
• 2004

This work proposes an 8b 220 MS/s 230 mW 3-stage pipeline CMOS ADC with on-chip filers for temperature- and power- insensitive voltage references. The proposed RC low-pass filters improve switching noise performance and reduce reference settling time at heavy R & C loads without conventional off-chip large bypass capacitors. The prototype ABC fabricated in a 0.25 um CMOS occupies the active die area of 2.25 $\textrm{mm}^2$ and shows the measured DNL and INL of maximum 0.43 LSB and 0.82 LSB, respectively. The ADC maintains the SNDR of 43 dB and 41 dB up to the 110 MHz input at 200 MS/s and 220 MS/s, respectively, while the SNDR at the 500 MHz input is degraded as much as only 3 dB than the SNDR at the 110 MHz input.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2016.10a
• /
• pp.527-530
• /
• 2016

This paper presents curvature-compensated reference circuits operating under low-voltage condition and achieving low-power consumption with $0.35-{\mu}m$ standard CMOS process. The proposed circuit can operate under less than 1-V supply voltage by using MOS transistors operating in weak-inversion region. The simulation results shows a low temperature coefficient by using the proposed curvature compensation technique. It generates a graph-shape temperature characteristic that looks like a sine curve, not a bell-shape characteristic presented in other published BGRs without curvature compensation. The proposed circuits operate with 0.9-V supply voltage. First, the voltage reference circuit consumes 176nW power and the temperature coefficient is $26.4ppm/^{\circ}C$. The current reference circuit is designed to operate with 194.3nW power consumption and $13.3ppm/^{\circ}C$ temperature coefficient.