• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.2
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• pp.106-111
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• 2015

Since most reference voltage generator circuits have bi-stable characteristics, it is important to employ a proper start-up circuit to operate a reference generator in the desired state. In this paper, we propose a start-up circuit for a low voltage reference generator. This start-up circuit determines the state of the circuit reliably by measuring the current drawn by BJTs in the circuit, which is well-defined in the desired state. To measure the current using CMOS-compatible devices only, a comparator with an internal offset voltage is used. The reliability of the proposed circuit is confirmed by Monte-Carlo simulations of the start-up operation, which show that, with the proposed start-up circuit, the low voltage reference generator starts reliably with supply voltages over 850mV even in the presence of device mismatches.

• The Transactions of the Korean Institute of Power Electronics
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• v.3 no.4
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• pp.407-411
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• 1998

Traditional carrier-based PWM method cannot produce maximum output voltage due to dead-time compensation, w which results in degradation of voltage utilization factor compared with ideal PWM inverters, Dual-carrier PWM has b been proposed as an alternative method to solve this problem. But this method requires paying attentition to changing r reference voltage in the vicinity of maximum voltage to ensure enough dead-time. Novel dual-carrier PWM method and i it's practical implementation is proposed in this paper. The reference voltage can be changed without any restriction in t this method.

• Proceedings of the KIEE Conference
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• 2006.07a
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• pp.210-211
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• 2006

본 논문은 무효전력 특성에 따라 나누어진 각 지역의 대표 pilot bus 전압을 기준으로 계통 전압을 제어함으로 계통 내에 모든 버스 전압을 통한 제어보다 효율적인 방법을 제시한다. Pilot bus 전압을 기준으로 하는 경우는 계통내 모든 버스의 전압을 기준으로 하는 경우에 비해 필요로 하는 정보의 양이 작을 것이므로 더 효율적이라고 할 수 있다. 본 논문에서는 IEEE 14 버스 시스템에서 특정 상정사고가 일어났을 경우를 가정으로 steady state voltage monitoring and control(SSVMC)를 통한 전압제어 시뮬레이션을 하였다. 모든 버스 전압을 기준으로 한 경우와 pilot bus 전압을 기준으로 SSVMC해준 경우를 비교 제시하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.458-461
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• 2015

In this paper 2 types of voltage references and a current reference suitable for low-voltage, low-power circuits are proposed and designed with $0.35{\mu}m\;CMOS$ process. MOS transistors operating in weak inversion and bulk-driven technique are utilized to achieve low-voltage and low-power features. The first voltage reference consumes 1.43uA from a supply voltage of 1.2V while it has a reference voltage of 585mV and a TC(Temperature Coefficient) of $6ppm/^{\circ}C$. The second voltage reference consumes 48pW from a supply voltage of 0.3V while having a reference voltage of 172mV and a TC of $26ppm/^{\circ}C$. The current reference consumes 246nA from a supply voltage of 0.75V with a reference current of 32.6nA and a TC of $262ppm/^{\circ}C$. The performances of the designed references have been verified through simulations.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.123-125
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• 2007

포항가속기연구소가 추진 중인 제4세대 방사광가속기에는 100 PPM급의 클라이스트론 펄스전압 안정도가 요구된다. 이러한 안정도는 PFN(pulse forming network)에 충전되는 전압을 얼마나 정밀하게 제어하는가에 따라서 결정된다. PFN의 최종운전 전압은 deQing circuit에 triggering되는 시점에 따라서 결정된다. DeQing trigger system은 PFN의 충전전압과 기준전압을 비교하여 충전전압이 기준전압보다 커지는 시점에서 charging choke(충전 쵸크)의 2차에 구성된 deQing 회로의 SCR를 트리거 시켜서 충전 쵸크 1차와 2차의 권선비율이 25:1인 충전 쵸크의 2차를 단락시켜 1차에 흐르는 전류를 2차로 빼주어서 PFN 커패시터에 더 이상 충전되지 않게 하는 구조로 되어있다. DeQing circuit에 triggering되는 시점을 정밀하게 제어하기 위하여 PFN 충전전압을 미분하여 그 출력전압에 비례하여 트리거 출력을 지연시키는 기능과 analog 신호를 digital 신호로 변환하는 기능을 사용하였다. 이 논문에서는 deQing 시스템에 관련된 회로 및 시험결과에 대하여 설명하고자 한다.

• Proceedings of the KIEE Conference
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• 2015.07a
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• pp.1020-1021
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• 2015

본 논문에서는 상용전압 AC 220V를 인가전압으로 사용하여 PMIC(Power Management IC)의 구동에 적합한 전압을 인가해주는 Pre-Regulator를 설계하였다. 설계된 Pre-Regulator는 상용전압을 사용하기 때문에 Device의 내압이 700V인 Magnachip $0.35{\mu}m$ BCD 공정을 이용하여 설계되었으며, 회로의 구성은 저전압 입력 보호 기능 및 JFET의 구동 제어를 위한 Under Voltage Lock Out(UVLO)회로, 전압조정기(Regulator)의 기준전압을 생성해주는 밴드갭 기준전압 발생(Bandgap Reference)회로, LDO(Low Drop Out)회로로 구성되어있다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.8
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• pp.1552-1557
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• 2007

In this work, temperature stable pulse width modulation controller using bandgap reference voltage is proposed. Two bandgap reference voltages are designed by using BiCMOS technology which are temperature dependent and independent voltage references. PWM controller is designed by using 3.3 volt supply voltage and the output frequency is 1MHz. From simulation results, the variation of output pulse width is less than form +0.86% to -0.38% in the temperature range $0^{\circ}C\;to\;70^{\circ}C$.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.143_144
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• 2009

본 논문은 우리나라 전력계통의 345kV 변전소에 대한 전압운영기준을 제시하여 준다. 전압운영기준을 개발하기 위해 2차 전압제어이론을 적용하였고, 지역구분을 위해서는 CESI 알고리즘을 사용하였다. 본 검토에 사용된 계통검토용 PSS/E 기본파일은 실계통 운전실적 데이터를 사용하였고, 지역별 대표모선에 대한 기준전압은 최적조류계산을 사용하여 계산하였다. 각 제어지역별 전압범위와 제어기준들은 다양한 조건하에서의 EMS 운전실적 데이터 분석을 통해 제시되었다.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.5
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• pp.851-858
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• 2017

In this study, the voltage control system of a single phase full bridge inverter was designed based on the SPWM driving method. The voltage control system consists of a single-phase full-bridge inverter, a PI controller for linearly compensating the error between the reference voltage and the output voltage, a PWM driving circuit for generating the gate signal using the SPWM method from the controller signal, and an LC filter for filtering the inverter output voltage waveform into sinusoidal waveform. Finally, the voltage control system of a single-phase full-bridge inverter based on the PWM driving method was modeled using EMTP-RV and by showing that the output voltage accurately converges the reference voltage through several simulation examples, the validity of the control system design was verified.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.375-378
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• 2013

A reference voltage generator which is insensitive to PVT (process-voltage-temperature) variation necessary for NVM memory IPs such as EEPROM and MTP memories is designed in this paper. The designed BGR (bandgap reference voltage) circuit based on MagnaChip's $0.18{\mu}m$ EEPROM process uses a low-voltage bandgap reference voltage generator of cascode current-mirror type with a wide swing and shows a reference voltage characteristic insensitive to PVT variation. The minimum operating voltage is 1.43V and the VREF sensitivity against VDD variation is 0.064mV/V. Also, the VREF sensitivity against temperature variation is $20.5ppm/^{\circ}C$. The VREF voltage has a mean of 1.181V and its three sigma ($3{\sigma}$) value is 71.7mV.