• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.706-713
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• 2010

In this paper, the small loop antenna with a parasitic loop structure for penta-band mobile phone application is proposed. This antenna is composed of a feed monopole, a radiating loop antenna with a parasitic loop structure and an additional radiating element. The antenna is printed on the very thin flexible substrate to mount on the dielectric carrier with a volume of 40 mm$\times$11 mm$\times$3 mm. The bandwidth of the proposed antenna is 402 MHz(773~1,175 MHz) for low band and 583 MHz(1,622~2,205 MHz) for high band. As a result, the proposed antenna covers the five bands of GSM850, GSM900, DCS1800, PCS1,900 and WCDMA for a 3:1 VSWR. Moreover, the radiation pattern, gain and efficiency are appropriate for mobile handset. Therefore, this antenna is suitable for small sized multi-band mobile handset applications.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.48 no.11
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• pp.873-880
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• 2020

In this paper, we propose a guidance filter to estimate line of sight rate with strapdown seeker measurements and INS(Inertial Navigation System) information. The measurements of proposed guidance filter consisted of the LOS(Line of Sight) and relative position that can be calculated with the seeker's measurements, INS information and known target position, also the filter is based on an asynchronous filter to use outputs of the two sensors that are out of synchronous and period. Through the proposed filter, we can reduce the effect on parasitic loop that can be caused by using large time delay seeker and improve the estimation performance.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.1 s.116
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• pp.24-30
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• 2007

A windmill-shaped loop antenna is designed for polarization diversity. Its circumference is almost 10 times that of a conventional small loop antenna whose circumference is less than ${\lambda}/10$ but its the radiation pattern is omni-directional. An identical parasitic element is placed over the radiator to match the antenna input impedance. An equivalent transmission line and RLC circuit models are shown to fully describe for the windmill-shaped loop antenna. The proposed antenna has a bandwidth of 6 % with input VSWR less than 2:1 and a polarization purity of 15 dB at 2.6 GHz, and the gain of 1.5 dBi. The simulated and measured results show fairly good agreement.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.6
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• pp.550-557
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• 2003

In this paper, two dualband internal antennas for GPS/PCS handset are proposed. At first, the monopole antenna with parasitic dipole element is designed to print PCB of handset directly. At second, the antenna with bended loop structure is designed to bend to use internal space of handset maximumly. The proposed dualband internal antennas provide a 2:1 VSWR bandwidth of over 19.1 % which are possible to cover two bands at once. the antennas have a gain between -0.4 and 3.33 ㏈i at all bands and they have almost omni-directional patterns.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.3
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• pp.195-203
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• 2020

This paper presents a parasitic inductance reduction design method for the stable driving of GaN HEMT. To reduce the parasitic inductance, we propose a vertical lattice loop structure with multiple loops that is not affected by the GaN HEMT package. The proposed vertical lattice loop structure selects the reference loop and designs the same loop as the reference loop by layering. The design reverses the current direction of adjacent current paths, increasing magnetic flux cancellation to reduce parasitic inductance. In this study, we validate the effectiveness of the parasitic inductance reduction method of the proposed vertical lattice loop structure.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.1
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• pp.80-83
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• 2017

In this paper, the X-band reconfigurable frequency selective surface having flexible geometry was proposed. The proposed RFSS is composed of patterns of cross-shaped loop with inductive stub, which can control the frequency response for C-Band and X-band by ON/OFF state of PIN diode. To minimize the parasitic effect and to obtain the high level of isolation between the unit cell of FSS and the bias circuit, we designed the grid type bias line on bottom layer through via hole. The measured transmission characteristics show good agreement with the simulation results and good stability of frequency response for different incident angles and curvatures of surface.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.9
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• pp.13-21
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• 2011

In this paper, the CMOS programmable interface circuit for MEMS gyroscope is presented, and evaluated with the MEMS sensing element. The circuit includes the front-end charge amplifier with 10 bit programmable capacitor arrays, 9 bit DAC for accurate offset calibration, and 10 bit PGA for accurate gain calibration. The self oscillation loop with automatic gain control operates properly. The offset error and gain error after calibration are measured to be 0.36 %FSO and 0.19 %FSO, respectively. The noise equivalent resolution and bias instability are measured to be 0.016 deg/sec and 0.012 deg/sec, respectively. The calibration capability of this circuit can reduce the variations of the output offset and gain, and this can enhance the manufacturability and can improve the yield.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.4A
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• pp.439-446
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• 2004

This paper describes high speed and low power design techniques for an 8-bit 500MSamples/s CMOS 2-step ADC. Instead of the conventional closed-loop architecture, the newly proposed ADC adopts open-loop architecture and uses a reset-switch to reduce loading time in an environment of big parasitic-capacitances of mux-array. An analog-latch is also used to reduce power consumption. Simulation result shows that the ADC has the SNDR of 46.91㏈ with a input frequency of 103MHz at 500Msample/s and consumes 203㎽ with a 1.8V single power supply. The chip is designed with a 0.18mm 1-poly 6-metal CMOS technology and occupies active area of 760${\mu}{\textrm}{m}$*800${\mu}{\textrm}{m}$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.5
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• pp.435-443
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• 2009

In this paper, we propose a microstrip slot antenna that works in Bluetooth, Zigbee, WiMAX and WLAN frequency bands($2.4{\sim}5.825\;GHz$). To get the wide bandwidth from the microstrip antenna proposed, we insert a pair of parastic strips along the feed line on the FR-4 dielectric substance(${\varepsilon}_r=4.8$). Furthermore, a simple geometrical rotation with quadrilateral slot is designed to maximize the bandwidth and to gain a wider frequency band than the conventional rectangular slot antenna. A additional design of the loop type is added to a cactus-shaped patched for 2.4 GHz ISM frequency band. The total measured bandwidth of the antenna is from 2.4 GHz to 6 GHz and the maximum gains of the antenna are 3.82 dBi, 4.48 dBi, 6.41 dBi and 6.65 dBi at the frequencies of 2.4 GHz, 3.5 GHz, 5.25 GHz and 5.77 GHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.19-24
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• 2007

With recent advancement of high-speed, multi-gigabit data transmission capabilities, serial links have been more widely adopted in industry than parallel links. Since the parallel link design forces its transmitter to transmit both the data and the clock to the receiver at the same time, it leads to hardware's intricacy during high-speed data transmission, large power consumption, and high cost. Meanwhile, the serial links allows the transmitter to transmit data only with no synchronized clock information. For the purpose, clock and data recovery circuit becomes a very crucial key block. In this paper, a 5.4Gbps half-rate bang-bang CDR is designed for the applications of high-speed graphic DRAM interface. The CDR consists of a half-rate bang-bang phase detector, a current-mirror charge-pump, a 2nd-order loop filter, and a 4-stage differential ring-type VCO. The PD automatically retimes and demultiplexes the data, generating two 2.7Gb/s sequences. The proposed circuit is realized in 66㎚ CMOS process. With input pseudo-random bit sequences (PRBS) of $2^{13}-1$, the post-layout simulations show 10psRMS clock jitter and $40ps_{p-p}$ retimed data jitter characteristics, and also the power dissipation of 80mW from a single 1.8V supply.