• Korean Journal of Optics and Photonics
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• v.20 no.1
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• pp.41-47
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• 2009

We report the spectral characteristics of Multimode Interferometer (MMI)-coupled semicondoctor square ring resonators. The epitaxial layers of the proposed semiconductor ring resonator consists of $1.55{\mu}m$ GaInAsP-InP multiple quantum wells. The lasing characteristics were observed by varying the structure parameters of the MMI-coupled square ring resonators. It is concluded that the MMI-coupled scheme selects a single spectral lasing mode in the double square ring cavities.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.1
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• pp.35-41
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• 2000

This paper considers the consturction of 24/25 I-NRZI (Interleaved - Non Return to Zero Inverse) modulator designs for DVCR (Digital Video Cassette Recorder), and size of validity bit in order to store the amplitude value of square-wave and the standard data ( sine and cosine coefficients) at ROM Table that to acceptable the spectrum standard. The validity bit size of the standard data and the amplitude value of square-wave that to store at ROM Table are affected the size of pilot signal on the output spectrum, and the hardware size of modulator. At the designable 24/25 I-NRZI modulator, we simulated using random pattern (F0,F1,F2) that to verification the output data of the spectrum. Moreover, the resultant of the spectrum analysis, at the optimizing value, is 0.065 on the amplitude value of square-wave, and 3bit on the size of bit in order to store the standared data at ROM Table. In order to verify the hardware of designable 24/25 I-NRZI modulator, we perform to modeling of C-language firstly, and coding to Verilog HDL (Cadence Verilog XL) and synthesized using Synopsys (Library "Samsung KG75") tool as a base of spectrum results. In a foundation of this result, we are considered the size of hardware. In this paper, a considerable 24/25 I-NRZI modulator designable less than 10,000 gates as that is improved consturction as regards the path method of pre-coder etc, and able to application digital camcorders as now practical use.

• Journal of the Korean Institute of Telematics and Electronics
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• v.17 no.3
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• pp.26-35
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• 1980

The degradation of image due to the finite size of sensing devices has been one of the problems in all digital imaging systems. The basic study on the improvement of the spatial resolution was carried out in both spatial and frequency domains by the resolution recovery techniques which have been used in optics. Here, the techniques were applied to CT (Computerized Tomography) system, and image with finer resolution was obtained by these techniques. The basic theory is described and the results of the simulation are shown.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1803-1804
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• 2008

이 논문에서는 임의의 크기를 가진 외란과 모델 불확실이 포함된 2관성계 시스템의 강인 제어기를 설계하고자 한다. 제안된 제어기는 역진 제어 기법을 사용하여, 2-관성계 시스템의 제어하고자 하는 상태 변수의 궤적과 공칭 궤적 사이의 오차를, 정상 상태에서뿐만 아니라 과도 상태에서도 임의의 크기로 줄일 수 있도록 설계될 것이다. 또한 비선형 제어 기법의 일종인 역진 제어 기법을 사용하였지만, 제시된 제어기의 구조는 시불변 선형 상태 궤환(state-feedback) 및 앞먹임(feedforward)의 구조를 가지게 되어 산업용 로봇에 적용될 수 있다는 장점을 가지고 있다. 실제로 이 논문에서는 제어기의 안정성에 대한 증명뿐만 아니라, 실제 로봇에 적용한 결과가 포함될 것이다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.6
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• pp.599-604
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• 2002

In this paper, a digital potentiometer is used as a load resistor of a wireless optical differential detector with a polarizer, to improve the noise reduction capability. In this structure, the noise voltages of the two photodiodes are made equal by controlling a digital potentiometer and the optical noise is cancelled out. With a digital potentiometer, the signal to noise ratio is enhanced by about 23 dB.

• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.15-17
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• 2018

엑티브 클램프 포워드 컨버터는 고효율, 간단한 구조의 특징으로 PC 파워 시스템, 서버 파워 시스템과 같은 어플리케이션에 많이 사용 되고 있다. 특히 더블 앤디드 엑티브 클램프 포워드 컨버터는 작은 출력 필터와 고효율의 장점이 있으나, 변압기 오프셋 전류로 인해 변압기의 크기와 코어 손실이 증가하게 된다. 본 논문에서는 새로운 게이트 신호 조정을 통해 낮은 변압기 오프셋 전류를 갖는 새로운 더블 앤디드 엑티브 클램프 포워드 컨버터를 제안한다. 따라서 변압기의 크기와 코어 손실, 1차측과 출력 인덕터의 전력손실이 감소함으로써 높은 전력밀도와 고효율을 달성하게 된다.

• Journal of the Korean Magnetics Society
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• v.14 no.2
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• pp.65-70
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• 2004

Read out signal and temperature distribution of magnetic amplifying magnetooptical disk were studied. Temperature distribution of recording layer and adjacent layers were calculated when the disk was at rest. Mark size, length and location were simulated from a chain of recording beam pulses. In addition, signal amplitude depending on the shape of the marks, readout signals from the recording layer and amplified marks of the readout layer, were simulated. Simplified thermal conduction model was used to calculate the temperature distribution of recording and adjacent layers as a function of time as well as to calculate the mark size, length and location. Readout signal was calculated by the convolution of the disk reflectivity and the Gaussian beam intensity. Readout signal from the mark in the readout layer amplified to the size of the laser beam fumed out to be twice as large as the signal from the crescent shaped mark in the recording layer.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.4
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• pp.225-234
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• 2003

Turbo compressors need high speed rotating impeller in structure, high rate gearbox and conventional induction motor. This mechanical system increased moment of inertia and mechanical friction loss. Recently turbo compressor has adopted a super high-speed motor and driver and have made its size smaller and mechanical friction loss at minimum. In this paper, variable super high - speed motor controller, compressor controller and MMI controller are implemented with only one DSP (TMS320VC33) chip for a 150HP, 70,000rpm direct drive turbo compressor. It was required hardware and software integration. The result of integration, Controller hardware became simple and all control software are developed same developing tool. The implements turbo compressor meets the requirements.

• The Journal of the Korea Contents Association
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• v.16 no.3
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• pp.91-101
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• 2016

This paper presents the design of new parallel BCH decoder for MLC NAND flash memory. The proposed decoder supports the multi-byte parallel operations to enhance its throughput. In addition, it employs a LFSR-based parallel syndrome generator for compact hardware design. The proposed BCH decoder is synthesized with hardware description language, VHDL and it is verified using Xilinx FPGA board. From the simulation results, the proposed BCH decoder enhances the throughput by 2.4 times than its predecessor employing byte-wise parallel operation. Compared to the other counterpart employing a GFM-based parallel syndrome generator, the proposed BCH decoder requires the same number of cycles to complete the given works but the circuit size is reduced to less than one-third.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.2
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• pp.97-103
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• 2009

In this paper, the performance of a hybrid value predictor according to the instruction fetch rate on window size superscalar processors is evaluated. In general, the data dependency relations of instructions are increased with the number of the fetched instructions. Therefore, it is expected that the performance of a value predictor will be higher when the instruction fetch rate is increased. The performance is studied for the machine with collapsing buffer and he one with trace cache as an instruction fetch mechanism. As a result of experiment, it is showed that the performance effect of a value predictor is higher as the instruction fetch rate of instruction window size, IPC, predict rate on apply with non-tc and tc is increased.