The Journal of the Institute of Internet, Broadcasting and Communication (한국인터넷방송통신학회논문지)

The Institute of Internet, Broadcasting and Communication (한국인터넷방송통신학회)
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Hybrid Value Predictor in Wide-Issue Superscalar Processor

슈퍼스칼라 프로세서에서 명령 윈도우 크기에 따른 혼합형 값 예측기

  • Received : 2009.03.18
  • Published : 2009.04.30
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Abstract

In this paper, the performance of a hybrid value predictor according to the instruction fetch rate on window size superscalar processors is evaluated. In general, the data dependency relations of instructions are increased with the number of the fetched instructions. Therefore, it is expected that the performance of a value predictor will be higher when the instruction fetch rate is increased. The performance is studied for the machine with collapsing buffer and he one with trace cache as an instruction fetch mechanism. As a result of experiment, it is showed that the performance effect of a value predictor is higher as the instruction fetch rate of instruction window size, IPC, predict rate on apply with non-tc and tc is increased.

본 논문에서는 슈퍼스칼라에서 윈도우 크기에 따른 명령 페치율에 따라 혼합형 값 예측기의 성능을 평가한다. 일반적으로, 명령의 데이터 의존성은 명령의 페치수에 따라 증가된다. 그러므로, 명령 페치율이 증가할 때 값 예측기의 성능이 높다고 본다. 이러한 성능은 명령 페치 메카니즘인 컬랩싱 버퍼와 트레이스 캐쉬로 연구한다. 실험결과는 명령 윈도우 크기에 따른 명령 페치율 증가와 혼합형에서 non-tc 와 tc을 적용한 IPC와 예측률의 값 예측기의 성능 효과를 평가한다.

Keywords

References

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