• Journal of Chest Surgery
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• v.30 no.11
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• pp.1055-1061
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• 1997

In the field of the experimental lung transplantation, we analyzed the CT findings of acute rejection, infection in the left single allotransplanted lung of adult mongrel dogs, and the CT findings were compared with the histological findings obtained by the lung biopsy Twenty two adult mongrel dogs were divided into two groups(Donor and recipient group). Donor lungs were flushed with LPDG(low pota,ilium dextral glucose) solution(n=4) or modified Euro-collins solution(n=7) and preserved over 20 hours with $10^{\circ}C(1$ case preservation for 4hours). After left single lung transplantation, the chest X-ray and sequential computed tomogram were performed with concomitant hemodynamic study and arterial blood gas analysis on immediate postoperative period, postoperative 3rd day and postoperative 7th day. Two of eleven transplanted lungs had acute rejection which was represented as moderate infiltration at immediate or 1st postoperative d y but became extensive infiltration at postoperative 3rd day on CT. There were showed one case of bronchopleural fistula, six cases of pneumonia and two cases of pulmonary infarction. In one rejection cases, the opacity of transplanted lung was improved by injection of methylprednisolone 500mg daily during 3 days. We concluded that CT was a useful noninvasive evaluation parameter after lung transplantation and the serial CT scan enabled early detection of acute rejection.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.6
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• pp.470-476
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• 2020

In this paper, we present the design of modular replaceable AI server for image deep learning that separates the server from the Edge Device so as to drive the AI block and the method of data transmission and reception. The modular replaceable AI server for image deep learning can reduce the dependency between social robots and edge devices where the robot's platform will be operated to improve drive stability. When a user requests a function from an AI server for interaction with a social robot, modular functions can be used to return only the results. Modular functions in AI servers can be easily maintained and changed by each module by the server manager. Compared to existing server systems, modular replaceable AI servers produce more efficient performance in terms of server maintenance and scale differences in the programs performed. Through this, more diverse image deep learning can be included in robot scenarios that allow human-robot interaction, and more efficient performance can be achieved when applied to AI servers for image deep learning in addition to robot platforms.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1113-1124
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• 2004

In this paper, we proposed a hardware(H/W) structure which can compress and recontruct the input image in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into H/W with the efficient structure for FPGA. We used the DWT(discrete wavelet transform) which transforms the data from spatial domain to the frequency domain, because use considered the motion JPEG2000 as the application. The implemented H/W is separated to both the data path part and the control part. The data path part consisted of the image processing blocks and the data processing blocks. The image processing blocks consisted of the DWT Kernel fur the filtering by DWT, Quantizer/Huffman Encoder, Inverse Adder/Buffer for adding the low frequency coefficient to the high frequency one in the inverse DWT operation, and Huffman Decoder. Also there existed the interface blocks for communicating with the external application environments and the timing blocks for buffering between the internal blocks The global operations of the designed H/W are the image compression and the reconstruction, and it is operated by the unit of a field synchronized with the A/D converter. The implemented H/W used the 69%(16980) LAB(Logic Array Block) and 9%(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70MHz clock frequency. So we verified the real time operation of 60 fields/sec(30 frames/sec).

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.2
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• pp.608-616
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• 2018

If a general nonlinear system is linearized by the successive multiplication of the 1st and 2nd order systems, then there are four types of poles in this linearized system: the pole of the 1st order system and the equal poles, two distinct real poles, and complex conjugate pair of poles of the 2nd order system. Linear Quadratic (LQ) control is a method of designing a control law that minimizes the quadratic performance index. It has the advantage of ensuring the stability of the system and the pole placement of the root of the system by weighted matrix adjustment. LQ control by the weighted matrix can move the position of the pole of the system arbitrarily, but it is difficult to set the weighting matrix by the trial and error method. This problem can be solved using the characteristic equations of the Hamiltonian system, and if the control weighting matrix is a symmetric matrix of constants, it is possible to move several poles of the system to the desired closed loop poles by applying the control law repeatedly. The paper presents a method of calculating the state weighting matrix and the control law for moving the equal poles with Jordan blocks to two real poles using the characteristic equation of the Hamiltonian system. We express this characteristic equation with a state weighting matrix by means of a trigonometric function, and we derive the relation function (${\rho},\;{\theta}$) between the equal poles and the state weighting matrix under the condition that the two real poles are the roots of the characteristic equation. Then, we obtain the moving-range of the two real poles under the condition that the state weighting matrix becomes a positive semi-finite matrix. We calculate the state weighting matrix and the control law by substituting the two real roots selected in the moving-range into the relational function. As an example, we apply the proposed method to a simple example 3rd order system.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.2
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• pp.585-594
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• 2018

Virtual currencies have emerged along with new technologies such as block chain, artificial intelligence (AI), and big data. This study examines the benefits of a security-enhanced block chain resulting from individual trading, decentralized from governments, as well as the problems associated with misuse of virtual currencies. Virtual currencies, due to its anonymity, is vulnerable to financial crimes, such as ransom-ware, fraud, drug trafficking, tax evasion and money laundering. Use of virtual currencies can facilitate criminals avoid detection from investigative agencies. Government regulatory policy continues to address these concerns, and the virtual currency exchange has also announced a self-regulation proposal. However, a fundamental solution remains necessary. The purpose of this paper is to investigate the problems regarding abuse of virtual currency and to identify a practical system for transactions involving virtual currencies. However, in order to promote transactions involving virtual currencies and to institutionalize a governance system, multilateral cooperation is required. Although the restricting the use of virtual currencies regarding minors and foreign trade, as well as the introduction of a real-name system are considered promising prospects, many problems remain. Virtual currency is not a simple digital item but a method of redesigning the function of money. Coordinated efforts are needed globally to be able to further activate the positive aspects concerning the use of virtual currencies.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.64-72
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• 2012

Synchronization including timing recovery, frequency offset compensation, and frame synchronization is most important signal processing block in all wireless/wired communication systems. In most communication systems, synchronization schemes based on training sequences or preambles are used. WLAN standards of 802.11a/g/n released by IEEE are based on OFDM systems. OFDM systems are known to be much more sensitive to frequency and timing synchronization errors than single carrier systems. A loss of orthogonality between the multiplexed subcarriers can result in severe performance degradations. The starting position of the frame and the beginning of the symbol and training symbol can be estimated using correlation methods. Correlation processing functionality is usually complex because of large number of multipliers in implementation especially when the reference signal is non-binary. In this paper, a simple correlation based synchronization scheme is proposed for IEEE 802.11a/g/n systems. Existing property of a periodicity in the training symbols are exploited. Simulation and implementation results show that the proposed method has much smaller complexity without any performance degradation than the existing schemes.

• Journal of KIISE
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• v.45 no.1
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• pp.53-60
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• 2018

This study describes a spatial web object retrieval system using Spark, an in - memory based distributed processing system. Development of social networks has created massive amounts of spatial web objects, and retrieval and analysis of data is difficult by using exist spatial web object retrieval systems. Recently, development of distributed processing systems supports the ability to analyze and retrieve large amounts of data quickly. Therefore, a method is promoted to search a large-capacity spatial web object by using the distributed processing system. Data is processed in block units, and one of these blocks is converted to RDD and processed in Spark. Regarding the discussed method, we propose a system in which each RDD consists of spatial web object index for the included data, dividing the entire spatial region into non-overlapping spatial regions, and allocating one divided region to one RDD. We propose a system that can efficiently use the distributed processing system by dividing space and increasing efficiency of searching the divided space. Additionally by comparing QP-tree with R-tree, we confirm that the proposed system is better for searching the spatial web objects; QP-tree builds index with both spatial and words information while R-tree build index only with spatial information.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.71-80
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• 2007

This paper describes an efficient hardware design of WiBro security processor (WBSec) supporting for the security sub-layer of WiBro wireless internet system. The WBSec processor, which is based on AES (Advanced Encryption Standard) block cipher algorithm, performs data oncryption/decryption, authentication/integrity, and key encryption/decryption for packet data protection of wireless network. It carries out the modes of ECB, CTR, CBC, CCM and key wrap/unwrap with two AES cores working in parallel. In order to achieve an area-efficient implementation, two design techniques are considered; First, round transformation block within AES core is designed using a shared structure for encryption/decryption. Secondly, SubByte/InvSubByte blocks that require the largest hardware in AES core are implemented using field transformation technique. It results that the gate count of WBSec is reduced by about 25% compared with conventional LUT (Look-Up Table)-based design. The WBSec processor designed in Verilog-HDL has about 22,350 gates, and the estimated throughput is about 16-Mbps at key wrap mode and maximum 213-Mbps at CCM mode, thus it can be used for hardware design of WiBro security system.

• Journal of IKEEE
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• v.14 no.2
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• pp.1-8
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• 2010

In this paper, Green Mode Power IC is designed to reduce the standby power. The proposed and designed IC works for the Switch Mode Power Supply(SMPS) and has the function of PWM. To reduce the unnecessary electric power, burst mode and skip mode section are introduced and controlled by external power MOSFET to diminish the standby power. The proposed IC is designed and simulated by KEC 30V-High Voltage 0.5um CMOS Process. The structure of proposed IC is composed of voltage regulator circuit, voltage reference circuit, UVLO(Under Voltage Lock out) circuit, Ibias circuit, green circuit, PWM circuit, OSC circuit, protection circuit, control circuit, and level & driver circuit. Measuring the current consumption of each block from the simulation results, 1.2942 mA of the summing consumption current from each block is calculated and ot proved that it is within the our design target of 1.3 mA. The current consumption of the proposed IC in this paper is less than a half of conventional ICs, and power consumption is reduced to the extent of 1W in standby mode. From the above results, we know that efficiency of proposed IC is superior to the previous IC.

• The KIPS Transactions:PartD
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• v.13D no.3 s.106
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• pp.399-404
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• 2006

A real-time system is used for various systems from small embedded systems to distributed enterprise systems. Because it has a characteristic that provides a service on time, developers should make efforts to keep this property about time when developing real-time applications. As the result of research about real-time system indicates, TMO model supports various functions for time processing according to the real-time concept. And it guarantees response time which developers defined. So developers need a point of reference to define deadline and check the correctness of time. This paper proposes an improved PS-Block as an infrastructure of analysis tools for TMO to present a point of reference. There is a problem that the existing PS-Block has overhead caused by a policy making duplicated blocks. As such, this paper implements a PS-Block Timing Model to reduce the overhead due to block duplication, and defines a base class for searching in PS-Block. The PS-Block Timing Model, using an improved PS-Block structure, offers a point of reference of deadline and an infrastructure of execution time analysis according to the PS-Block configuration policy. Therefore, TMO developers can easily verify deadline of real-time methods, and improve reliability, and reduce development terms.