• Title/Summary/Keyword: 근사비

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State-Matching Properties and Stability of Redesigned Fuzzy Digital Control System (근사 이산화 모델들을 이용한 재설계된 퍼지 디지털 제어시스템의 상태-정합 특성 몇 안정도)

  • Kim, Do-Wan;Ju, Yeong-Hun;Park, Jin-Bae
    • Proceedings of the Korean Institute of Intelligent Systems Conference
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    • 2007.04a
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    • pp.409-412
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    • 2007
  • 본 논문에서는 근사 이산-시간 모델 기반 지능형 디지털 재설계 기법의 타당성에 대해서 논의한다. 타당성을 검증하기 위해 재설계된 디지털 제어 퍼지 시스템의 안정도 및 상태-정합에 특성이 분석된다. 구체적으로 근사 이산-시간 모델들의 상태 사이의 비정합의 크기가 충분히 작으면 재설계된 디지털 제어 퍼지 시스템의 평형점은 점근적 안정함을 보인다. 또한 이러한 비정합이 영으로 수렴함에 따라 재설계된 디지털 제어 퍼지 시스템과 주어진 아날로그 제어시스템 사이의 비정합은 매우 작아짐을 보인다.

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A study on the sliding rigid indentor over the viscoelastic layer supported by the elastic half-space (탄성체로 기대된 점잔성체층에서의 강성체의 운동해석)

  • Nam, J. W.
    • Journal of the korean Society of Automotive Engineers
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    • v.5 no.3
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    • pp.56-63
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    • 1983
  • 강성체로된 견인물체가 탄성무한경면으로 지지된 점탄성층 위를 미끄러져 갈 때 접촉구간에서의 압력분포와 마찰 특성을 고찰하였다. 즉, 접촉구간에서의 강성체의 모양과 압력분포에 관한 적분 방정식을 구하고, 점탄성층의 두께가 접촉구간에 비하여 충분히 두꺼울 때 압력분포와 마찰계 수의 근사해를 구하였다. 압력분포의 모양은 점탄성층의 물성을 표시하는 지수값, 즉 .alpha.<1/2, .alpha.=1/2, .alpha.>1/2에 따라서 크게 다르다. 한편, 수치해석에 의하면 마찰 계수에 대한 근 사해는 강성체의 미끄럼 속도, 점탄성 층의 두께, 탄성체의 영율 (E$_{o}$ )과 점탄성층의 시효 성탄성계수 (E$_{v}$ )의 차, 즉 E$_{o}$ /E$_{v}$ 에 따라 변화함을 알 수 있다. 즉, 탄성체가 점탄성층에 비하여 딱딱하면 할수록, 또 강성체 속도가 느리면 느릴수록 마찰계수는 작아진다. 그리고 불성의 지수(.alpha.)가 커지면 커질수록 근사해의 수렵 속도는 느려지게 되고 지 수(.alpha.)가 1에 가까워지면 점탄성층의 탄성효과는 점성효과에 비하여 거의 무시할 수 있으며 근사해는 의미가 없어지게 된다.

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An Optimal COG Defuzzifier Design Using Lamarckian Co-adaptation (라마키안 상호 적응에 의한 최적 COG 비퍼지화기 설계)

  • 김대진;이한별
    • Proceedings of the Korean Institute of Intelligent Systems Conference
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    • 1998.10a
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    • pp.390-396
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    • 1998
  • 본 논문은 퍼지 논리 제어기(FLC)의 근사화 능력과 제어 성능을 동시에 향상시키는 정확한 무게 중심(Center Of Gravity; COG) 비퍼지화기를 제안한다. 본 논문은 비퍼지화 과정이 최적 선택의 한 과정이며 비퍼지화 방법의 적절한 선택이다. 제안한 COG 비퍼지화기의 정확성은 출력 소속 함수를 여러 개의 설계 파라메터(중신, 폭, 변경자(modifier))로 나타내고 이들 설계 파라메터들을 학습과 진화의 Lamarckian 상호 적응에 의하여 갱신함으로써 얻어진다. 이러한 학습과 진화의 상호 적응은 학습하지 않는 경우 보다 빠르게 최적 COG 비퍼지화기를 얻도록 하며, 보다 넓은 범위의 탐색으로최적해를 찾을 가능성을 높여 준다. 제안한 설계 방법은 목적 함수의 가중치를 조절하여 높은 근사화 능력, 높은 제어 성능, 또는 이들간의 균형된 성능을 갖는 다양한 특정 응용형(Application-specific)COG 비퍼지화기를 제공한다. 제안한 상호적응 COG 비퍼지화기의 설계방법을 트럭 후진 주차 제어 문제에 적용하여, 각각 시스템 오차와 평균 추적 거리로 나타내어진 근사화 능력과 제어 성능을 기존의 COG 비퍼지화기와 비교한다.

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Adaptive Fuzzy Sliding Mode Control for Nonlinear Systems Using Estimation of Bounds for Approximation Errors (근사화 오차 유계 추정을 이용한 비선형 시스템의 적응 퍼지 슬라이딩 모드 제어)

  • Seo Sam-Jun
    • Journal of the Korean Institute of Intelligent Systems
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    • v.15 no.5
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    • pp.527-532
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    • 2005
  • In this paper, we proposed an adaptive fuzzy sliding control for unknown nonlinear systems using estimation of bounds for approximation errors. Unknown nonlinearity of a system is approximated by the fuzzy logic system with a set of IF-THEN rules whose consequence parameters are adjusted on-line according to adaptive algorithms for the purpose of controlling the output of the nonlinear system to track a desired output. Also, using assumption that the approximation errors satisfy certain bounding conditions, we proposed the estimation algorithms of approximation errors by Lyapunov synthesis methods. The overall control system guarantees that the tracking error asymptotically converges to zero and that all signals involved in controller are uniformly bounded. The good performance of the proposed adaptive fuzzy sliding mode controller is verified through computer simulations on an inverted pendulum system.

A 10-bit 10-MS/s Asynchronous SAR analog-to-digital converter with digital-to-analog converter using MOM capacitor (MOM 커패시터를 사용한 디지털-아날로그 변환기를 가진 10-bit 10-MS/s 비동기 축차근사형 아날로그-디지털 변환기)

  • Jeong, Yeon-Ho;Jang, Young-Chan
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.1
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    • pp.129-134
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    • 2014
  • This paper presents a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) which consists of a digital-to-analog converter (DAC), a SAR logic, and a comparator. The designed asynchronous SAR ADC with a rail-to-rail input range uses a binary weighted DAC using metal-oxide-metal (MOM) capacitor to improve sampling rate. The proposed 10-bit 10-MS/s asynchronous SAR ADC is fabricated using a 0.18-${\mu}m$ CMOS process and its active area is $0.103mm^2$. The power consumption is 0.37 mW when the voltage of supply is 1.1 V. The measured SNDR are 54.19 dB and 51.59 dB at the analog input frequency of 101.12 kHz and 5.12 MHz, respectively.

Development of MLS Difference Method for Material Nonlinear Problem (MLS차분법을 이용한 재료비선형 문제 해석)

  • Yoon, Young-Cheol
    • Journal of the Computational Structural Engineering Institute of Korea
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    • v.29 no.3
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    • pp.237-244
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    • 2016
  • This paper presents a nonlinear Moving Least Squares(MLS) difference method for material nonlinearity problem. The MLS difference method, which employs strong formulation involving the fast derivative approximation, discretizes governing partial differential equation based on a node model. However, the conventional MLS difference method cannot explicitly handle constitutive equation since it solves solid mechanics problems by using the Navier's equation that unifies unknowns into one variable, displacement. In this study, a double derivative approximation is devised to treat the constitutive equation of inelastic material in the framework of strong formulation; in fact, it manipulates the first order derivative approximation two times. The equilibrium equation described by the divergence of stress tensor is directly discretized and is linearized by the Newton method; as a result, an iterative procedure is developed to find convergent solution. Stresses and internal variables are calculated and updated by the return mapping algorithm. Effectiveness and stability of the iterative procedure is improved by using algorithmic tangent modulus. The consistency of the double derivative approximation was shown by the reproducing property test. Also, accuracy and stability of the procedure were verified by analyzing inelastic beam under incremental tensile loading.

A Study on the LQG/LTR for Nonminimum Phase Plant (II) : Realization for the Optimal Approximation Method (비 최소위상 플랜트에 대한 LQG/LTR에 관한 연구(II) : 최적 근사 방법의 실현)

  • 강진식;서병설
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.16 no.10
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    • pp.981-991
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    • 1991
  • LQG/LTR method suggested to improve robustness of LQG have a theoritical constraint that it cannot apply to nonminimum phase plant(NMP). In this paper, we suggest a new LQG/LTR method for NMP which consist of three design steps. The first step is design a additional feed-foward compensator which approximate the given NMP plant to minimum phase(MP) plant and the next step is design a target loop transfer function for approximated MP plant satisfying the design specifications such as robust-performance and robust-stability. The last step is loop transfor recovery(LTR) that the open loop transfer function recovers the terget loop. It was shown by simulation example that the suggested method can solve the NMP constraint in designing LQG/LTR.

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Approximation Vertex Search of Polygon-based Shape Coding by the Type of Distortion Patterns (왜곡 패턴 유형에 의한 다각형 기반 형상 부호화의 근사 정점 탐색)

  • Seo Jeong-Gu;Kwak No-Yoon;Seo Beom-Seok;Hwang Byong-Won
    • Journal of Digital Contents Society
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    • v.3 no.2
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    • pp.197-209
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    • 2002
  • If we reduce the number of vertexes to decrease bit rate in polygon-based shape coding, the distortion of approximated contour increases rapidly. On the other hand, if we reduce the distortion, the number of vertexes increases rapidly and many bits are required to encode the vertexes. To improve this problem, in this paper we propose the approximation vertex search method. The encoder in the proposed method searches the type of distortion patterns that is the most similar to the shape which polygon edge and contour segment form and then encodes it. And then, the decoder mathematically finds the approximated vertexes from decoded distortion pattern information. Therefore, the proposed algorithm results in encoding many vertexes at a low bit rate and having the smoother shape than conventional method. As shown in computer simulation, the proposed method has less distortion than conventional method. It costs less bit rate by $10{\sim}20%$ than conventional algorithm in same distortion.

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ECG signal compression based on B-spline approximation (B-spline 근사화 기반의 심전도 신호 압축)

  • Ryu, Chun-Ha;Kim, Tae-Hun;Lee, Byung-Gook;Choi, Byung-Jae;Park, Kil-Houm
    • Journal of the Korean Institute of Intelligent Systems
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    • v.21 no.5
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    • pp.653-659
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    • 2011
  • In general, electrocardiogram(ECG) signals are sampled with a frequency over 200Hz and stored for a long time. It is required to compress data efficiently for storing and transmitting them. In this paper, a method for compression of ECG data is proposed, using by Non Uniform B-spline approximation, which has been widely used to approximation theory of applied mathematics and geometric modeling. ECG signals are compressed and reconstructed using B-spline basis function which curve has local controllability and control a shape and curve in part. The proposed method selected additional knot with each step for minimizing reconstruction error and reduced time complexity. It is established that the proposed method using B-spline approximation has good compression ratio and reconstruct besides preserving all feature point of ECG signals, through the experimental results from MIT-BIH Arrhythmia database.

Approximate Multiplier with High Density, Low Power and High Speed using Efficient Partial Product Reduction (효율적인 부분 곱 감소를 이용한 고집적·저전력·고속 근사 곱셈기)

  • Seo, Ho-Sung;Kim, Dae-Ik
    • The Journal of the Korea institute of electronic communication sciences
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    • v.17 no.4
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    • pp.671-678
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    • 2022
  • Approximate computing is an computational technique that is acceptable degree of inaccurate results of accurate results. Approximate multiplication is one of the approximate computing methods for high-performance and low-power computing. In this paper, we propose a high-density, low-power, and high-speed approximate multiplier using approximate 4-2 compressor and improved full adder. The approximate multiplier with approximate 4-2 compressor consists of three regions of the exact, approximate and constant correction regions, and we compared them by adjusting the size of region by applying an efficient partial product reduction. The proposed approximate multiplier was designed with Verilog HDL and was analyzed for area, power and delay time using Synopsys Design Compiler (DC) on a 25nm CMOS process. As a result of the experiment, the proposed multiplier reduced area by 10.47%, power by 26.11%, and delay time by 13% compared to the conventional approximate multiplier.