• Journal of Advanced Navigation Technology
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• v.24 no.2
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• pp.107-114
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• 2020

A power amplifier of 2.4 GHz ISM band is designed to implement a transmitter system. High efficiency amplifiers can be implemented as class E or class F amplifiers. This study has designed a 20 W high efficiency class E amplifier that has simple circuit structure in order to utilize for the ISM band application. The impedance matching circuit was designed by class E design theory and circuit simulation. The designed amplifier has the output power of 44.2 dBm and the power added efficiency of 69% at 2.45 GHz. In order to apply 30 dBm input power to the designed power amplifier, voltage controlled oscillator (VCO) and driving amplifier have been fabricated for the input feeding circuit. The measurement of the power amplifier shows 43.2 dBm output and 65% power added efficiency. This study can be applied to the design of power amplifiers for various wireless communication systems such as wireless power transfer, radio jamming device and high power transmitter.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.3
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• pp.380-388
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• 2011

In this paper, we developed the X-band 63 watt pulsed SSPA(Solid State Power Amplifier) by using HMIC(Hybrid Microwave Integrated Circuits). The pulsed SSPA consists of power supply and 3-stage amplifier modules : pre-amplifier stage, driver-amplifier stage, final-amplifier stage. The developed pulsed SSPA provides more than 63 watts of output power with a short pulse width and the duty cycle of up to 1.2 % at $70^{\circ}C$. The fabricated module offers great than 37 dB of saturated gain across the operating band. Input and output VSWR is <1.5:1. This module has an average current of 400 mA typical and operates at a +28 $V_{dc}$ supply. The developed SSPA in this paper can apply to pulsed Doppler radar with high speed operation.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.2
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• pp.72-75
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• 2012

In this paper, high-efficiency DC-AC converter is implemented for the wireless power transmission. The DC-AC converter is implemented by combining the oscillator and power amplifier. Because the conversion efficiency of wireless power transmitter is strongly affected by the efficiency of power amplifier, the high-efficiency power amplifier is implemented by using the Class-E amplifier structure. Also, because the output power of oscillator connected to the input stage of power amplifier is low, high-gain two-stages power amplifier using the drive amplifier is implemented to realize the high-output power DC-AC converter. The dual band harmonic suppression filter is implemented to suppress 2nd, 3rd harmonics of 13.56 MHz. The output power and conversion efficiency of DC-AC converter are 40 dBm and 80.2 % at the operation frequency of 13.56 MHz.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.8
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• pp.1817-1823
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• 2009

A design of cascaded distributed amplifier with a broadband amplification is described in this paper. A medium power device with 23dBm, max output power under the optimal narrow-band power matching condition is adopted for the design and fabrication of the cascaded distributed amplifier. In general, conventional distributed amplifiers with the parallel connected input ports have a low gain, and previous cascaded distributed amplifiers show a relatively low output power of 10dBm at most, which is the upper limit of small signal amplification. However, the cascaded distributed amplifier in this paper shows the gain of $18.15{\pm}0.75dB$ and output power of 20dBm over $300MHz{\sim}2GHz$ from the measurement, so it can be well adopted as a wideband driver amplifier.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.1
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• pp.50-54
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• 2011

In this article, the linearity of single power amplifier is improved by suppress $2^{nd}$ and $3^{rd}$ harmonics at output port of high power amplifier and by cancelling of $3^{rd}$ IMD. The matching network in order to suppress harmonics consists of metamaterial like the CRLH. The $2^{nd}$ and $3^{rd}$ harmonics are suppressed over 27 dBc, respectively. A phase of generated $3^{rd}$ IMD at output of DPA (drive power amplifier) has changed in order to offset the $3^{rd}$ IMD of HPA (high power amplifier). The harmonics of the proposed PAM suppress over 6 dB than single HPA. The PAM has a 36.98 dBm of the output power, 21.6 dB of the power gain and 29.4 % of the PAE. The harmonics is a -53 dBc about PAM. This result indicate that a harmonic level is lower 20 dB than reference power amplifier.

• Journal of Satellite, Information and Communications
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• v.5 no.2
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• pp.82-86
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• 2010

In this paper, a power amplifier module for WCDMA base-station applications is designed and implemented using GaN field-effect transistors (FETs), which uses an envelope tracking bias system. The designed module consists of an high gain MMIC amplifier, a driver amplifier, a power amplifier, and bias circuits for envelope tracking applications. Especially, a FET bias sequencing circuit and two isolators are integrated for stable RF operations. All circuits are assembled within a single housing, so its dimension is just $17.8{\times}9.8{\times}2.0\;cm3$. Measured results show that the developed power amplifier module has good envelope tracking capability: the power-added efficiency of 35% at the output power range from 30dBm to 40dBm over a wide range of drain bias.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.6
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• pp.726-732
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• 2019

In this study, we proposed an asymmetric differential inductor to improve the linearity of differential power amplifiers. Considering the phase error between differential signals of the differential amplifier, the location of the center tap of the differential inductor was modified to minimize the error. As a result, the center tap was positioned asymmetrically inside the differential inductor. With the asymmetric differential inductor, the AM-to-AM and AM-to-PM distortions of the amplifier were suppressed. To confirm the feasibility of the inductor, we designed a 2.4 GHz differential CMOS PA for IEEE 802.11n WLAN applications with a 64-quadrature amplitude modulation (QAM), 9.6 dB peak-to-average power ratio (PAPR), and a bandwidth of 20 MHz. The designed power amplifier was fabricated using the 180-nm RF CMOS process. The measured maximum linear output power was 17 dBm, whereas EVM was 5%.

• Journal of Advanced Navigation Technology
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• v.10 no.2
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• pp.167-172
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• 2006

In this paper, the 25W power amplifier for UHF band radio transceiver has been designed and realized. The power amplifier was composed of drive, power amplifier and control stages. Feedback topology and coaxial line baluns were used for wide band operation. The VDMOS, which has reliable performance for linearity and efficiency, was used for power device and designed to operate as push-pull amplification at Class AB Bias. The power amplifier designed in such a way was found to show stable AM modulation performance when voice signal was detected at the gate stage, with being designed and realized to meet output specifications of commercial air traffic control transmitter.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.5
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• pp.24-32
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• 2017

In this paper, a low power 4th order delta-sigma modulator was designed with a high resolution of 12 bits or more for the biological signal processing. Using time-interleaving technique, 4th order delta-sigma modulator was designed with one operational amplifier. So power consumption can be reduced to 1/4 than a conventional structure. To operate stably in the big difference between the two capacitor for kT/C noise and chip size, the variable-stage amplifier was designed. In the first phase and second phase, the operational amplifier is operating in a 2-stage. In the third and fourth phase, the operational amplifier is operating in a 1-stage. This was significantly improved the stability of the modulator because the phase margin exists within 60~90deg. The proposed delta-sigma modulator is designed in a standard $0.18{\mu}m$ CMOS n-well 1 poly 6 Metal technology and dissipates the power of $354{\mu}W$ with supply voltage of 1.8V. The ENOB of 11.8bit and SNDR of 72.8dB at 250Hz input frequency and 256kHz sampling frequency. From measurement results FOM1 is calculated to 49.6pJ/step and FOM2 is calculated to 154.5dB.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.10A
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• pp.1223-1229
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• 2004

A variable-gain low-voltage low noise amplifier MMIC operating at 5GHz frequency band is designed and implemented using the ETRI 0.5$\mu\textrm{m}$ GaAs MESFET library process. This low noise amplifier is designed to have the variable gain for adaptive antenna array combined in HIPERLAN/2. The feedback circuit of a resistor and channel resistance controlled by the gate voltage of enhancement MESFET is proposed for the variable-gain low noise amplifier consisted of cascaded two stages. The fabricated variable gain amplifier exhibits 5.5GHz center frequency, 14.7dB small signal gain, 10.6dB input return loss, 10.7dB output return loss, 14.4dB variable gain, and 2.98dB noise figure at V$\_$DD/=1.5V, V$\_$GGl/=0.4V, and V$\_$GG2/=0.5V. This low noise amplifier also shows-19.7dBm input PldB, -10dBm IIP3, 52.6dB SFDR, and 9.5mW power consumption.