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Study of Parallel Network Processor using Global Cache (글로벌 캐시를 이용한 네트워크 병렬 프로세서 구조 연구)

  • Park, Jae-Won;Chung, Won-Young;Kim, Hyun-Pil;Lee, Jung-Hee;Lee, Yong-Surk
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.36 no.1B
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    • pp.80-85
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    • 2011
  • The mount of network traffic from the Internet is increasing because of the use of Broadband Convergence Networks(BcN). Network traffic is also increasing because of the development of application, especially multimedia traffic from IPTV, VOD, and online games. This multimedia traffic not only has a huge payload but also should be considered a threat in real time. For this reason, this study examines the ways that routers distribute the bandwidth in accordance to traffic properties. To classify the property of the traffic, it is essential to analyze the application layer. However, the general network processor architecture serially processes the L2-4 and L7 layer. We propose a novel parallel network processor architecture with a global cache that processes L2-4 and L7 in parallel. To verify the proposed architecture, we simulated both of the architecture with SystemC. EEMBC and SNORT was used to measure L2-4 and L7 processing time. When multimedia traffic was entered into the network processor in the same flow, the proposed architecture showed about 85% higher performance than general architecture.

A 14b 100MS/s $3.4mm^2$ 145mW 0.18um CMOS Pipeline A/D Converter (14b 100MS/s $3.4mm^2$ 145mW 0.18un CMOS 파이프라인 A/D 변환기)

  • Kim Young-Ju;Park Yong-Hyun;Yoo Si-Wook;Kim Yong-Woo;Lee Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.5 s.347
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    • pp.54-63
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    • 2006
  • This work proposes a 14b 100MS/s 0.18um CMOS ADC with optimized resolution, conversion speed, die area, and power dissipation to obtain the performance required in the fourth-generation mobile communication systems. The 3-stage pipeline ADC, whose optimized architecture is analyzed and verified with behavioral model simulations, employs a wide-band low-noise SHA to achieve a 14b level ENOB at the Nyquist input frequency, 3-D fully symmetric layout techniques to minimize capacitor mismatch in two MDACs, and a back-end 6b flash ADC based on open-loop offset sampling and interpolation to obtain 6b accuracy and small chip area at 100MS/s. The prototype ADC implemented in a 0.18um CMOS process shows the measured DNL and INL of maximum 1.03LSB and 5.47LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 59dB and 72dB, respectively, and a power consumption of 145mW at 100MS/s and 1.8V. The occupied active die area is $3.4mm^2$.

A 30 GHz Band Low Noise for Satellite Communications Payload using MMIC Circuits (MMIC 회로를 이용한 위성중계기용 30GHz대 저잡음증폭기 모듈 개발)

  • 염인복;김정환
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.11 no.5
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    • pp.796-805
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    • 2000
  • A 30GHz band low noise amplifier module, which has linear gain of 30dB and noise figure of 2.6dB, for 30GHz satellite communication transponder was developed by use of MMIC and thin film MIC technologies. Two kinds of MMIC circuits were used for the low noise amplifier module, the first one is ultra low noise MMIC circuit and the other is wideband and high gain MMIC circuit. The pHEMT technology with 0.15$mu extrm{m}$ of gate length was applied for MMIC fabrication. Thin film microstrip lines on alumina substrate were used to interconnect two MMIC chips, and the thick film bias circuit board were developed to provide the stabilized DC bias. The input interface of the low noise amplifier module was designed with waveguide type to receive the signal from antenna directly, and the output port was adopted with K-type coaxial connector for interface with the frequency converter module behind the low noise amplifier module. Space qualified manufacturing processes were applied to manufacture and assemble the low noise amplifier module, and space qualification level of environment tests including thermal and vibration test were performed for it. The developed low noise amplifier was measured to show 30dB of minimum gain, $\pm$0.3dB of gain flatness, and 2.6dB of maximum noise figure over the desired operating frequency range from 30 to 31 GHz.

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Performance of CWDM Fabricated by the PLC-AWG Technology (평판형 AWG 기술을 이용한 광대역 파장다중화/역다중화 소자의 제작 및 특성)

  • Moon, H.M.;Kwak, S.C.;Hong, J.Y.;Lee, K.H.;Kim, D.H.;Kim, J.J.;Choi, S.Y.;Lee, J.G.;Lee, J.H.;Lim, K.G.;Kim, J.B.
    • Korean Journal of Optics and Photonics
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    • v.18 no.3
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    • pp.185-189
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    • 2007
  • A novel technology for CWDM (Coarse Wavelength Division Multiplexer) utilizing a PLC (Planar Lightwave Circuit)-AWG (Arrayed Waveguide Grating) fabrication process is proposed. BPM (Beam Propagation Method) Simulation results on the employed parabolic-horn-type input slab waveguide of AWG and the performance of the 20 nm-channel spacing CWDM with flattened passband are presented. Waveguides of $0.75{\triangle}%$ have been used in this experiment and the insertion loss at the peak wavelength is 3.5 dB for a Gaussian spectrum and is 4.8 dB for a flat-top spectrum. The bandwidth at 3 dB is better than 10 nm and 13 nm for Gaussian and flat-top spectra, respectively.

The basic experiments for the fabrication of the SPUDT type Inter using the SFIT type filter (SFIT형태를 이용한 SPUDT형 필터제작에 관한 기초실험)

  • You, Il-Hyun
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.11 no.10
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    • pp.1916-1923
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    • 2007
  • We have studied to obtain the SAW filter for the passband was formed on the Langasite substrate and was evaporated by Aluminum-Copper alloy and thin we performed computer-simulated by simulator. We cm fabricate that the block weighted type IDT as an input transducer of the filter and the withdrawal weighted type IDT as an output transducer of the filter from the results of our computer-simulation. Also, we have performed to obtain the properly design conditions about phase shift of the SAW filter for WCDMA. We have employed that the number of pairs of the input and output IDT are 50 pairs and the thickness and the width of reflector are $5000\;{\AA}$ and $3.6{\mu}m$ respectively. And we have employed that the distances from the hot electrode to the reflector are $2.0{\mu}m$, $2.4{\mu}m$ and the distance from the hot electrode to the ground is $1.5{\mu}m$ respectively. Frequency response of the fabricated SAW filter has the property that the center frequency is about 190MHz and bandwidth at the 3dB is probably 7,8MHz. And we could obtain that return loss is less then -18dB, ripple characteristics is probably 3dB and triple transit echo is less then -25dB after when we have matched impedance.

Research on Broadband Signal Processing Techniques for the Small Millimeter Wave Tracking Radar (소형 밀리미터파 추적 레이더를 위한 광대역 신호처리 기술 연구)

  • Choi, Jinkyu;Na, Kyoung-Il;Shin, Youngcheol;Hong, Soonil;Park, Changhyun;Kim, Younjin;Kim, Hongrak;Joo, Jihan;Kim, Sosu
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.21 no.6
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    • pp.49-55
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    • 2021
  • Recently, a small tracking radar requires the development of a small millimeter wave tracking radar having a high range resolution that can acquire and track a target in various environments and disable the target system with a single blow. Small millimeter wave tracking radar with high range resolution needs to implement a signal processor that can process wide bandwidth signals in real time and meet the requirements of small tracking radar. In this paper, we designed a signal processor that can perform the role and function of a signal processor for a small millimeter wave tracking radar. The signal processor for the small millimeter wave tracking radar requires the real-time processing of input signal of OOOMHz center frequency and OOOMHz bandwidth from 8 channels. In order to satisfy the requirements of the signal processor, the signal processor was designed by applying the high-performance FPGA (Field Programmable Gate Array) and ADC (Analog-to-digital converter) for pre-processing operations, such as DDC (Digital Down Converter) and FFT (Fast Fourier Transform). Finally, the signal processor of the small millimeter wave tracking radar was verified via performance test.

Scalable Video Coding using Super-Resolution based on Convolutional Neural Networks for Video Transmission over Very Narrow-Bandwidth Networks (초협대역 비디오 전송을 위한 심층 신경망 기반 초해상화를 이용한 스케일러블 비디오 코딩)

  • Kim, Dae-Eun;Ki, Sehwan;Kim, Munchurl;Jun, Ki Nam;Baek, Seung Ho;Kim, Dong Hyun;Choi, Jeung Won
    • Journal of Broadcast Engineering
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    • v.24 no.1
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    • pp.132-141
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    • 2019
  • The necessity of transmitting video data over a narrow-bandwidth exists steadily despite that video service over broadband is common. In this paper, we propose a scalable video coding framework for low-resolution video transmission over a very narrow-bandwidth network by super-resolution of decoded frames of a base layer using a convolutional neural network based super resolution technique to improve the coding efficiency by using it as a prediction for the enhancement layer. In contrast to the conventional scalable high efficiency video coding (SHVC) standard, in which upscaling is performed with a fixed filter, we propose a scalable video coding framework that replaces the existing fixed up-scaling filter by using the trained convolutional neural network for super-resolution. For this, we proposed a neural network structure with skip connection and residual learning technique and trained it according to the application scenario of the video coding framework. For the application scenario where a video whose resolution is $352{\times}288$ and frame rate is 8fps is encoded at 110kbps, the quality of the proposed scalable video coding framework is higher than that of the SHVC framework.

A design method for optical fiber filter of lattice structure (격자형 광파이버필터의 설계에 관한 연구)

  • 이채욱;문병현;김신환
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.18 no.9
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    • pp.1248-1256
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    • 1993
  • The propagation and delay properties in opical fiber are particularly attractive because digital signal processing and conventional analog signal processing techniques such as those using surface acoustic wave devices are limited In their usefulness for signal bandwidth exceeding one or two GHz, although they are very effective at lower frequencies. Since an accurate, low loss and short time delay elements can be obtained by using such an optical fiber, optical signal precessing has attracted much attention for high speed and broad-band signal precessing in particular channel separation filtering for optical FDM signals. In this paper, we consider a coherent optical lattice filter, which uses coherent light sources and consists of directional couplers and optical fiber delay elemnts. The optical fiber fitters are more restricted than the usual digital filters. The reasons are as follows. 1) the coupling coefficients of directional couplers are restricted to the number between 0 and 1. 2) optical signal E(complex amplitude) is divided into J If-$\boxUl$ and J L/7$\div$$\boxUl$ at the directional coupler. Considering these restrictions and in this case all the coupling coefficients of summing and branching elements are set to be equal, we have given design formulae for optical lattice filter, which make the best use of optical signal energy.

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A Study on the Shaped-Beam Antenna with High Gain Characteristic (고이득 특성을 갖는 성형 빔 안테나에 대한 연구)

  • Eom, Soon-Young;Yun, Je-Hoon;Jeon, Soon-Ick;Kim, Chang-Joo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.18 no.1 s.116
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    • pp.62-75
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    • 2007
  • This paper describes a shaped-beam antenna for increasing the antenna gain of a radiating element. The proposed antenna structure is composed of an exciting element and a multi-layered disk array structure(MDAS). The stack micro-strip patch elements were used as the exciter for effectively radiating the electromagnetic power to the MDAS over the broadband, and finite metallic disk array elements - which give the role of a director for shaping the antenna beam with the high gain - were finitely and periodically layered onto it. The efficient power coupling between the exciter and the MDAS should be carried out in such a way that the proposed antenna has a high gain characteristic. The design parameters of the exciter and the MDAS should be optimized together to meet the required specifications to meet the required specifications. In this study, a shaped-beam antenna with high gain was optimally designed under the operating conditions with a linear polarization and the frequency band of $9.6{\sim}10.4\;GHz$. Two methods constructed using thin dielectric film and dielectric foam materials respectively were also proposed in order to implement the MBAS of the antenna. In particular, through the computer simulation process, the electrical performance variations of the antenna with the MDAS realized by the thin dielectric film materials were shown according to the number of disk array elements in the stack layer. Two kinds of antenna breadboard with the MDAS realized with the thin dielectric film and dielectric foam materials were fabricated, but experimentation was conducted only on the antenna breadboard(Type 1) with the MDAS realized with the thin dielectric film materials according to the number of disk array elements in the stack layer in order to compare it with the electrical performance variations obtained during the simulation. The measured antenna gain performance was found to be in good agreement with the simulated one, and showed the periodicity of the antenna gain variations according to the stack layer number of the disk array elements. The electrical performance of the Type 1 antenna was measured at the center frequency of 10 GHz. As the disk away elements became the ten stacks, a maximum antenna gain of 15.65 dBi was obtained, and the measured return loss was not less than 11.4 dB within the operating band. Therefore, a 5 dB gain improvement of the Type 1 antenna can be obtained by the MDAS that is excited by the stack microstrip patch elements. As the disk array elements became the twelve stacks, the antenna gain of the Type 1 was measured to be 1.35 dB more than the antenna gain of the Type 2 by the outer dielectric ring effect, and the 3 dB beam widths measured from the two antenna breadboards were about $28^{\circ}$ and $36^{\circ}$ respectively.