• Proceedings of the Korean Information Science Society Conference
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• 2008.06b
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• pp.456-459
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• 2008

공정 기술의 발전에 따라 공정 변이 (process variation)에 따른 수율 (yield) 감소 문제가 대두하고 있으며, 공정 변이 대응 설계 기법 (process variation tolerant design technique)은 하드웨어 제작 시 반드시 고려되어야 할 중요한 요소가 되었다. 캐시 메모리 (cache memory)의 경우에도 공정 변이로 인한 수율 감소 문제에 대처할 수 있는 설계 방법의 개발이 절실하다. 본 논문에서는 캐시에 저장되는 데이터의 특성 분석을 통해 공정 변이에 대응할 수 있는 새로운 캐시 구조 설계에 대한 연구를 소개한다.

• Proceedings of the Korean Institute Of Construction Engineering and Management
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• 2006.11a
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• pp.515-518
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• 2006

Construction project has various effective factor and many producer in multifarious process of the work. Thus it has many variation. However, Process management up to now is management method of conclusion oriented. So, it do not consider sequency and variation occurrence. In a result that a lot of problems happen. Lean Construction can solve limit of the present management method. And Lean Construction is estimated new management method of process management for reliance on process plan, safety of process and promotion of effectiveness. This study analysed application of real construction project in Lean Construction theory and examined to utilize VSM and TACT for field application.

• Korean Journal of Construction Engineering and Management
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• v.2 no.4 s.8
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• pp.117-126
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• 2001

The purpose of this study is to present a way of Variation Control in building construction process. The study suggest a way of the application method of shielding, decoupling concept and also Poka-yoke device to control variation that occurs from uncertainty in construction industry with lots of waste factors. The main contents of the study are as follows; (1) It's suggested strategy to apply shielding, decoupling as variation control technique. (2) Current Poka-yoke devices are investigated and analyzed. As a future research, it is required to study continuously on the more effective application method of Poka-yoke device and on existing examples in domestic construction sites for the process improvement.

• Proceedings of the Korean Institute Of Construction Engineering and Management
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• autumn
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• pp.257-260
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• 2001

Buffers, on which much research is being done, are being used as a means to alleviate impacts in processes. Impacts occur from variation which is caused by uncertainty. Current buffers just accept variation as it comes and have just been used as a means to reduce impact. The purpose of this research try to understand the assorted variations which arise from limited resources and information and then we present a division of buffers as the way to overcome these variations. Through the process of dividing buffers into screening buffers, pulling buffers, shielding buffers, and working buffers, we try to make the process more compact, eliminate unnecessary reduction, speed up the decision making process by excluding excessive information, and improve the reliability of work.

• 월간산업보건
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• s.335
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• pp.44-55
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• 2016

• 월간산업보건
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• s.353
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• pp.23-28
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• 2017

• Korean Journal of Construction Engineering and Management
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• v.2 no.4 s.8
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• pp.48-61
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• 2001

This study aims at improving work reliability. It proposes a way to overcome the limitations of current scheduling methods by providing a new framework, CPAM(Construction Process Analysis Model) based on the lean principles. It suggests methods which improve work reliability and production effectiveness with variability control methods. Also it suggests methods which reduce inventories of materials and equipment and WIP(Work In Process) using two techniques; Lookahead Schedule and Weekly Work Plan. The contribution of this research also includes that it assumes planning as a process of reducing uncertainty and maximizing throughput, counter-posing plan reliability to resource redundancy as alternative strategies for managing in conditions of uncertain work flow.

• Korean Journal of Construction Engineering and Management
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• v.10 no.2
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• pp.75-83
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• 2009

PPC stands for the percentage of weekly assignments completed. It makes it possible to improve the performance of production planning and control systems. Recently, the cases of PPC application have been increasing because PPC is easy to apply to construction site. However, to evaluate the average of PPC or analyze PPC as time passes has some problem ; if PPC is the same, the average it is evaluated equally although there are variabilities in production system. Therefore, In order to evaluate the character of PPC in process of production this paper suggests the method of the evaluating PPC by using coefficient of variability besides PPC measurement.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.7
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• pp.122-129
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• 2014

Due to remarkable market growth of smart devices, higher performance and more functionalities are required for a core system-on-chip (SoC), and thus the power demand is rapidly increasing. However, aggressive shrink of CMOS transistor have brought severe process variations thereby adversely affected the performance and power consumption under strict power constraint. Voltage binning (VB) scheme is one of the effective post silicon tuning techniques, which can reduce parametric yield loss due to process variations by adjusting supply voltage. In this paper, an optimal supply voltage tuning based voltage binning technique is proposed to reduce average power without an additional yield loss. Considering the different LVCC margins of process corners along with speed and leakage characteristics, the proposed method can optimize the deviation of voltage margin and thus save power consumption. When applying on a 30nm mobile SoC product, the experimental results showed that the proposed technique reduced average power consumption up to 6.8% compared to traditional voltage binning under the same conditions.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.59-65
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• 2013

Conventional synchronous design circuits cannot only satisfy the timing requirement of the low voltage digital systems, but also they may generate wrong outputs under the influence of PVT variations and aging effects. Therefore, in this paper, a NCL (Null Convention Logic) design as an asynchronous design method has been proposed, where the NCL method doesn't require any timing analysis, and it has a very simple design methodology. Base on the NCL method, a new low power reliable ALU has been designed and implemented using MagnaChip-SKhynix 0.18um CMOS technology. The experimental results of the proposed NCL ALU have been compared to those of a conventional pipelined ALU in terms of power consumption and speed.