• Proceedings of the Korean Information Science Society Conference
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• 2005.07a
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• pp.721-723
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• 2005

상위 단계 합성에서의 자원 공유 (또는 바인딩)는 최종회로 결과의 질에 심각한 영향을 미치는 중요한 작업들 가운데 하나이다. 기존의 자원 공유 기법의 목적은 주어진 자원 제약 조건하에서 회로의 지연 시간을 최소화하거나, 주어진 지연시간 조건하에서 하드웨어의 복잡도 (예: 회로 면적)를 최소화하는 것이다. 본 논문에서는, 자원 공유 문제를 회로에서 소모되는 전력 소모를 줄이는 각도에서 보고 있다. 구체적으로, 전압 배정 작업을 자원 공유 문제와 결합하여, 두 개의 작업을 통합된 방식으로 해결함으로서 회로 결과에서의 소모되는 전력 소모량을 충분히 그리고 효과적으로 줄이는데 목표를 두고 있다. 벤치마크를 사용한 실험에서 우리는 제안한 방법을 사용하면, 기존의 순차적인 자원 공유와 전압 배정 적용 방식보다 $0.7\%-16\%$ 더 적은 전력 소모를 가짐을 알 수 있었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.76-83
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• 2007

This paper describes a low power ROM using single charge-sharing capacitor and hierarchical bit line (SCSC-ROM). The SCSC-ROM reduces the power consumption in bit lines. It lowers the swing voltage of bit lines to a very small voltage by using a charge-sharing technique with a single capacitor. It implements the capacitor with dummy bit lines to improve noise immunity and make easy to design. The hierarchical bit line further saves the power by reducing the capacitance in bit lines. The SCSC-ROM also reduces the power consumption in control unit and predecoder by using the hierarchical word line decoder. The simulation result shows that the SCSC-ROM with $4K{\times}32bits$consumes only 37% power of a conventional ROM. A SCSC-ROM chip is fabricated in a $0.25{\mu}m$ CMOS process. It consumes 8.2mW at 240MHz with 2.5V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.99-105
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• 2004

A shared-capacitor charge-sharing ROM (SCCS-ROM) using dummy bit lines is proposed. The SCCS-ROM reduces the bit line swing voltage using the charge-sharing technique of the conventional charge-sharing ROM (CS-ROM). Although the CS-ROM needs three small capacitors per output bit, the proposed SCCS-ROM shares the capacitors so that it needs only three capacitors. The SCCS-ROM implements the capacitors using dummy bit lines. This not only increases noise immunity but also reduces power. A SCCS-ROM with 8K${\times}$15bits implemented in a 0.35${\mu}{\textrm}{m}$ CMOS process. The SCCS-ROM consumes 8.63㎽ at 100MHz with 3.3V The simulation results show that the SCCS-ROM reduces 8.4% power compared to the CS-ROM.

• Proceedings of the KAIS Fall Conference
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• 2004.11a
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• pp.131-133
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• 2004

이 논문에서는 MPEG audio 알고리즘의 필터뱅크를 덧셈을 사용하여 저전력으로 구현할 수 있는 구조를 제안하였다. 제안된 구조는 CSD(Canonic Signed Digit) 형의 계수를 사용하며, 입력신호 샘플을 최대로 공유함으로서 사용되는 덧셈기의 수를 최소화하였다. 제안된 구조는 알고리즘에서 사용된 공통입력 공유, 선형위상 대칭 필터계수를 이용한 공유, 공통입력을 이용한 블록 공유, CSD 형의 계수와 공통패턴 공유를 통하여 사용되는 덧셈의 수를 최소화할 수 있음을 보였다. Verilog-HDL 코딩을 통하여 시뮬레이션을 수행한 결과, 제안된 구조는 기존의 곱셈기 구조의 구현면적과 비교하여 $59.6\%$를 감소시킬 수 있음을 보였다. 또한 제안된 구조의 전력소모도 곱셈기 구조와 비교하여 $59.6\%$를 감소시킬 수 있음을 보였다. 따라서 곱셈기가 내장된 DSP 프로세서를 사용하지 않고도, Arithmetic Unit나 마이크로프로세서를 사용하여 효과적으로 MPEG audio 필터뱅크를 구현할 수 있음을 보였다.

• Proceedings of the IEEK Conference
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• 2003.07d
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• pp.1669-1672
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• 2003

본 논문은 공유자원과 태스크 활용률을 고려한 저전력 스케줄링 알고리즘을 제안한다. 기존에 공유자원을 고려한 논문에서는 선점 영역에서 최악실행시간만을 고려하였기 때문에 높은 전압을 계속 유지하여 전력 소비가 많고, 태스크들이 조기 종료할 경우 남는 시간을 활용하지 못하는 문제가 있다. 본 논문에서는 선점 영역에서는 태스크들이 조기 종료하는 경우 남는 시간을 이용하여 태스크 활용률을 갱신하고 다음 태스크에게 더 낮은 주파수와 전압을 인가하여 전력 소모를 줄이는 방법을 사용하고, 비 선점 영역에서는 최악 실행시간을 기준으로 한 최대 태스크 활용률을 이용하여 우선 순위 높은 태스크의 지연 시간을 최소화 시켜주는 방법을 제안한다. 실험 결과는 Arm8 테스트 벤치마크 데이터를 통해 기존의 알고리즘과 제안된 알고리즘의 전력 소모를 비교했을 때 6％의 파워 소모 감소를 보였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.7
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• pp.532-541
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• 2003

In a memory, most power is dissipated in high capacitive lines such as predecoder lines, word lines, and bit lines. To reduce the power dissipation in these high capacitive lines, this paper proposes three techniques using charge recycling and charge sharing. One is the charge recycling predecoder (CRPD). The second one is the charge recycling word line decoder (CRWD). The last one is the charge sharing bit line (CSBL) for a ROM. The CRPD and the CRWD recycle the previously used charge in predecoder lines and word lines. Theoretically, the power consumption in predecoder lines and word lines are reduced to a half. The CSBL reduces the swing voltage in the ROM bit lines to very small voltage using a charge sharing technique. the CSBL can significantly reduce the power dissipation in ROM bit lines. The CRPD, the CRWD, and the CSBL consume 82%, 72%, and 64% of the power of previous ROM designs respectively. A charge recycling and charge sharing ROM (CRCS-ROM) with the CRPD, the CRWD, and the CSBL is implemented. A CRCS-ROM with 8K16bits was fabricated in a 0.3${\mu}{\textrm}{m}$ CMOS process. The CRCS-ROM consumes 8.63㎽ at 100MHz with 3.3V. The chip core area is 0.1 $\textrm{mm}^2$.

• KIPE Magazine
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• v.27 no.2
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• pp.36-43
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• 2022

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.5
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• pp.283-290
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• 2004

In this paper, a low-power structure for 512 tap FIR filter in MPEG audio algorithm is proposed. By using CSD(Canonic Signed Digit) form filter coefficients and maximum sharing of input signal sample, it is shown that the number of adders of proposed structure can be minimized. To minimize the number of adders, the proposed structure utilizes the 4 steps of sharing, i.e., common input sharing, linear phase symmetric filter coefficient sharing, block sharing for common input, and common sub-expression sharing. Through Verilog-HDL coding, it is shown that reduction rates in the implementation area and relative power consumption of the proposed structure are 60.3% and 93.9% respectively, comparison to those of the conventional multiplier structure.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.3A
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• pp.221-228
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• 2009

We consider distributed resource allocation among the links in a wireless network to minimize the total transmit power of the network while meeting the target rate required by each link. The problem to be solved is how to change the amount of wireless resource allocated and the number of links sharing the resource according to the interference environment so that the following distributed power control game converges to a stable point. To provide a distributed method with less complexity and lower information exchange than the centralized optimal method, we define the resource sharing level among the links from which the size of resource allocated and the links sharing the resource are determined distributively. It is shown that the performance of the proposed method is better than that of the conventional methods, orthogonal resource allocation only and resource sharing only, as well as it approaches to that of the optimal method.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.13 no.6
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• pp.101-108
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• 2013

In this paper, we propose a method in which the negative acknowledge (NACK) message is used as command for cooperation and spectrum sharing. This allows for an automatic request for cooperation and sharing when the direct link of the primary user is in outage, and also allows for saving the number of control messages in cooperation-spectrum sharing based paradigm. In the sharing phase, the selected relay shares a power fraction of $1-{\alpha}$ for secondary transmitted signal while the remaining of ${\alpha}$ is for primary retransmitted signal. In the case of no relay collected, primary transmitter uses NACK as a command to retransmit the signal with fully power fraction (${\alpha}=1$). Both systems are assumed to employ BPSK signals. In this scheme, we propose the joint optimal decoding in the secondary user. The frame error rate (FER) performance at both systems is then analyzed. The theoretical and simulation results validate the analysis and confirm the efficiency of the protocol.