• The Mathematical Education
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• v.62 no.1
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• pp.1-21
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• 2023

The purpose of this study is to explore how the student, who interiorized three levels of units, constructed fractions as multipliers by analyzing her ways of conceiving improper fractions with three levels of units and coordinating two three-levels-of-units structures. Among the data collected from our teaching experiment with two 4th grade students meeting 13 times for three months, we focus on how Seyeon, one of the participating students, wrote numerical expressions in the form of "× fraction" for the given situations using her splitting operation for composite units. Given the importance of splitting operation for composite units for the construction of fractions as multipliers, implications for further research are discussed.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.6
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• pp.289-300
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• 2001

본 논문에서는 유한 필드 GF(2$_{m}$ ) 상에서 모듈러 곱셈 A($\chi$)B($\chi$) mod P($\chi$)을 수행하는 새로운 선형 문제-크기(full-size) 시스톨릭 어레이 구조인 LSB-first 곱셈기를 제안한다. 피연산자 B($\chi$)의 LSB(least significant bit)를 먼저 사용하는 LSB-first 모듈러 곱셈 알고리즘으로부터 새로운 비트별 순환 방정식을 구한다. 데이터의 흐름이 규칙적인 순환 방정식을 공간-시간 변환으로 새로운 시스톨릭 곱셈기를 설계하고 분석한다. 기존의 곱셈기와 비교할 때 제안한 곱셈기의 면적-시간 성능이 각각 10%와 18% 향상됨을 보여준다. 또한 같은 설계방법으로 곱셈과 제곱연산을 동시에 수행하는 새로운 시스톨릭 곱셈/제곱기를 제안한다. 유한 필드상의 지수연산을 위해서 제안한 시스톨릭 곱셈/제곱기를 사용할 때 곱셈기만을 사용 할 때보다 면적-시간 성능이 약 26% 향상됨을 보여준다.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.3
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• pp.50-58
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• 2013

In this paper, parallel decimal fixed-point multiplier which uses the limited range of Singed-Digit number encoding and the reduction step is proposed. The partial products are generated without carry propagation delay by encoding a multiplicand and a multiplier to the limited range of SD number. With the limited range of SD number, the proposed multiplier can improve the partial product reduction step by increasing the number of possible operands for multi-operand SD addition. In order to estimate the proposed parallel decimal multiplier, synthesis is implemented using Design Compiler with SMIC 180nm CMOS technology library. Synthesis results show that the delay of proposed parallel decimal multiplier is reduced by 4.3% and the area by 5.3%, compared to the existing SD parallel decimal multiplier. Despite of the slightly increased delay and area of partial product generation step, the total delay and area are reduced since the partial product reduction step takes the most proportion.

• Journal of the Korean School Mathematics Society
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• v.22 no.3
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• pp.303-327
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• 2019

This study proposed an integrated approach to multiplication as a way to help students understand multiplication in elementary mathematics. The integrated approach to multiplication is to give students a broad understanding of multiplication by solving a situation of multiplication in a variety of ways in mathematics classes, exploring and discussing each other's methods. The integrated approach to multiplication was derived from a number of previous studies that emphasized various approaches, a consistent approach, and a specific approach to multiplication. As results, the integrated approach of multiplication can be interpreted in four ways as a situation of multiplication, and each method is connected to important characteristics of multiplication emphasized in previous studies. In addition, this study has theoretically confirmed that the integrated approach to multiplication is important not only for multiplication but also for division, fraction and operation of fractions, ratios, rates, and proportions. This study is expected to provide some implications for teachers with regard to multiplication in elementary school mathematics.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.31 no.3
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• pp.473-480
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• 2021

To achieve the high-speed implementation of post-quantum cryptography, primitive operations should be tailored to the architecture of the target processor. In this paper, we present the optimized implementation of multiplier operation on RISC-V processor for post-quantum cryptography. Particularly, the column-wise multiplication algorithm is optimized with the primitive instruction of RISC-V processor, which improved the performance of 256-bit and 512-bit multiplication by 19% and 8% than previous works, respectively. Lastly, we suggest the instruction extension for the high-speed multiplication on the RISC-V processor.

• Education of Primary School Mathematics
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• v.25 no.1
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• pp.57-79
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• 2022

Current mathematics It is necessary to ensure that ratio and proportion concept is not distorted or broken while being treated as if they were easy to teach and learn in school. Therefore, the purpose of this study is to analyze the activities presented in the textbook. Based on prior work, this study reinterpreted the proportional reasoning task from the proportional perspective of Beckmann and Izsak(2015) to the multiplicative structure of Vergnaud(1996) in four ways. This compared how they interpreted the multiplicative structure and relationships between two measurement spaces of ratio and rate units and proportional expression and proportional distribution units presented in the revised textbooks of 2007, 2009, and 2015 curriculum. First, the study found that the proportional reasoning task presented in the ratio and rate section varied by increasing both the ratio structure type and the proportional reasoning activity during the 2009 curriculum, but simplified the content by decreasing both the percentage structure type and the proportional reasoning activity. In addition, during the 2015 curriculum, the content was simplified by decreasing both the type of multiplicative structure of ratio and rate and the type of proportional reasoning, but both the type of multiplicative structure of percentage and the content varied. Second, the study found that, the proportional reasoning task presented in the proportional expression and proportional distribute sections was similar to the previous one, as both the type of multiplicative structure and the type of proportional reasoning strategy increased during the 2009 curriculum. In addition, during the 2015 curriculum, both the type of multiplicative structure and the activity of proportional reasoning increased, but the proportional distribution were similar to the previous one as there was no significant change in the type of multiplicative structure and proportional reasoning. Therefore, teachers need to make efforts to analyze the multiplicative structure and proportional reasoning strategies of the activities presented in the textbook and reconstruct them according to the concepts to teach them so that students can experience proportional reasoning in various situations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.12
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• pp.1882-1889
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• 2021

This paper describes a high-performance hardware implementation of modular multiplication used as a core operation in elliptic curve cryptography. A 521-bit high-performance modular multiplier for NIST P-521 curve was designed by adopting 3-way Toom-Cook integer multiplication and fast reduction algorithm. Considering the property of the 3-way Toom-Cook algorithm in which the result of integer multiplication is multiplied by 1/3, modular multiplication was implemented on the Toom-Cook domain where the operands were multiplied by 3. The modular multiplier was implemented in the xczu7ev FPGA device to verify its hardware operation, and hardware resources of 69,958 LUTs, 4,991 flip-flops, and 101 DSP blocks were used. The maximum operating frequency on the Zynq7 FPGA device was 50 MHz, and it was estimated that about 4.16 million modular multiplications per second could be achieved.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.575-577
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• 2017

In public key cryptography such as RSA, modular exponentiation is the most time-consuming operation. RSA's modular exponentiation can be computed by repeated modular multiplication. To attain high efficiency for RSA, fast modular multiplication algorithms have been proposed to speed up decryption/encryption. Montgomery multiplication is limited by the carry propagation delay from the addition of long operands. In this paper, we propose a hardware structure that reduces the area of the Montgomery multiplication implementation for lightweight applications of RSA. Experimental results showed that the new design can achieve higher performance and reduce hardware area. A frequency of 884.9MHz and 250MHz were achieved with 84K and 56K gates respectively using the 90nm technology.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 2006.06a
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• pp.351-355
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• 2006

RSA 암호 시스템은 IC카드, 모바일 및 WPKI, 전자화폐, SET, SSL 시스템 등에 많이 사용된다. RSA는 모듈러 지수승 연산을 통하여 수행되며, Montgomery 곱셈기를 사용하는 것이 효율적이라고 알려져 있다. Montgomery 곱셈기에서 임계 경로 지연 시간(Critical Path Delay)은 세 피연산자의 덧셈에 의존하고 캐리 전파를 효율적으로 처리하는 문제는 Montgomery 곱셈기의 효율성에 큰 영향을 미친다. 최근 캐리 전파를 제거하는 방법으로 캐리 저장 덧셈기(Carry Save Adder, CSA)를 사용하는 연구가 계속 되고 있다. McIvor외 세 명은 지수승 연산에 최적인 CSA 3단계로 구성된 Montgomery 곱셈기와 CSA 2단계로 구성된 Montgomery 곱셈기를 제안했다. 시간 복잡도 측면에서 후자는 전자에 비해 효율적이다. 본 논문에서는 후자보다 빠른 연산을 수행하기 위해 캐리 전파 제거 특성을 가진 이진 부호 자리(Signed-Digit, SD) 수 체계를 사용한다. 두 이진 SD 수의 덧셈을 수행하는 잉여 이진 덧셈기(Redundant Binary Adder, RBA)를 새로 제안하고 Montgomery 곱셈기에 적용한다. 기존의 RBA에서 사용하는 이진 SD 덧셈 규칙 대신 새로운 덧셈 규칙을 제안하고 삼성 STD130 $0.18{\mu}m$ 1.8V 표준 셀 라이브러리에서 지원하는 게이트들을 사용하여 설계하고 시뮬레이션 하였다. 그 결과 McIvor의 2 방법과 기존의 RBA보다 최소 12.46%의 속도 향상을 보였다.

• School Mathematics
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• v.11 no.4
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• pp.685-706
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• 2009

This dissertation is aimed to investigate the reason why a contextualization is needed to help the meaningful teaching-learning concerning multiplications and divisions of fractions, the way to make the contextualization possible, and the methods which enable us to use it effectively. For this reason, this study intends to examine the differences of situations multiplying or dividing of fractions comparing to that of natural numbers, to recognize the changes in units by contextualization of multiplication of fractions, the context is set which helps to understand the role of operator that is a multiplier. As for the contextualization of division of fractions, the measurement division would have the left quantity if the quotient is discrete quantity, while the quotient of the measurement division should be presented as fractions if it is continuous quantity. The context of partitive division is connected with partitive division of natural number and 3 effective learning steps of formalization from division of natural number to division of fraction are presented. This research is expected to help teachers and students to acquire meaningful algorithm in the process of teaching and learning.