• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.7
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• pp.1289-1295
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• 2007

In this paper, we implemented high-performance concurrent control system which manages whole RF systems with digital type and communicates with remote station on both wire and wireless networking. It consists of FPGA (Field Programmable Gate Array) part which controls forward/reverse LPA (Linear Power Amplifier), forward/reverse LNA (Low Noise Amplifier), channel cut wire/wireless TCP/IP, etc, master microprocessor (AVR), which manages the whole control system, Slave microprocessor which communicates SA (Spectrum Analyzer) and observes frequency spectrum of each channel with the resolution of 5KHz, 10 channel card microprocessor which independently observes each channel card and sets frequency synthesizer in channel cut and other peripherals and logics. The whole system is divided to two parts of H/W (hardware) and S/W (software) considering operational efficiency and concurrency, and implementation and cost. H/W consists of FPGA and microprocessor. We expected the optimized operation through H/W and SW co-design and hybrid H/W architecture.

• Korean Journal of Optics and Photonics
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• v.14 no.3
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• pp.236-243
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• 2003

We discussed the design of lens module schematic eyes equivalent to finite model eyes, which are used to model the human eye based on spherical aberration and Stiles-Crowford effect. The optical system for head mounted display (HMD) is designed and evaluated using lens module schematic eyes. In addition to a compact HMD system, an optical system with high Performance is required. To satisfy these requirements, we used diffractive optical elements and aspheric surfaces so that the color and mono-chromatic aberrations were corrected. The optical system for HMD is composed of 0.47 inch micro-display of SVGA grade with 480,000 pixels, a plastic hybrid lens for the virtual image, and the lens module schematic eyes. The designed optical system fulfills the current specifications of HMD: such as, EFL of 31.25 mm, FOV of 24H$\times$18V$\times$30D degrees, and overall length of 59.1 mm. As a result, we could design an optical system useful for HMD; the system is expected to be comfortable while the user wears it.

• Journal of Digital Convergence
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• v.19 no.9
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• pp.257-269
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• 2021

The purpose of this study is to collect biosignal data in a non-invasive and non-restrictive manner using a BCG (Ballistocardiogram) sensor, and utilize artificial intelligence machine learning algorithms in ICT and high-performance computing environments. And it is to present and study a method for developing and validating a data-based blood glucose prediction model. In the blood glucose level prediction model, the input nodes in the MLP architecture are data of heart rate, respiration rate, stroke volume, heart rate variability, SDNN, RMSSD, PNN50, age, and gender, and the hidden layer 7 were used. As a result of the experiment, the average MSE, MAE, and RMSE values of the learning data tested 5 times were 0.5226, 0.6328, and 0.7692, respectively, and the average values of the validation data were 0.5408, 0.6776, and 0.7968, respectively, and the coefficient of determination (R²) was 0.9997. If research to standardize a model for predicting blood sugar levels based on data and to verify data set collection and prediction accuracy continues, it is expected that it can be used for non-invasive blood sugar level management.

• Applied Chemistry for Engineering
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• v.30 no.1
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• pp.23-28
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• 2019

We report a supercapacitor cable, which consists of three-dimensional (3D) porous graphene coated onto the surface of carbon thread. The 3D porous framework of graphene was constructed by microwave-activated process using a graphene oxide-coated carbon thread. The use of microwave irradiation enabled to convert graphene oxide into reduced graphene oxide without any reducing agents and activate graphene sheets into exfoliated and porous graphene sheets. Combining two wire electrodes with a polymer gel electrolyte successfully completed supercapacitor device in a form of cable construction. The supercapacitor cables were highly flexible, and thus can be transformed into various shapes of devices and be integrated into textile items. A high area-capacitance of 38.1 mF/cm was obtained at a scan rate of 10 mV/s. This capacitance was retained 88% of its original value at 500 mV/s. The cycle life was also demonstrated by repeating a charge/discharge process during 10,000 cycles even under bent states, showing a high capacitance retention of 96.5%.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.1
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• pp.173-180
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• 2022

Approximate Computing is a promising method for designing hardware-efficient computing systems. Approximate multiplication is one of key operations used in approximate computing methods for high performance and low power computing. An approximate 4-2 compressor can implement hardware-efficient circuits for approximate multiplication. In this paper, we propose an approximate multiplier with low area and low power characteristics. The proposed approximate multiplier architecture is segmented into three portions; an exact region, an approximate region, and a constant correction region. Partial product reduction in the approximation region are simplified using a new 4:2 approximate compressor, and the error due to approximation is compensated using a simple error correction scheme. Constant correction region uses a constant calculated with probabilistic analysis for reducing error. Experimental results of 8×8 multiplier show that the proposed design requires less area, and consumes less power than conventional 4-2 compressor-based approximate multiplier.

• Korean Journal of Optics and Photonics
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• v.34 no.6
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• pp.283-288
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• 2023

We investigate the optical and electrical properties of silver nanofilms deposited on transparent substrates such as quartz, sapphire, and slide glass treated with (3-mercaptopropyl) trimethoxysilane (MPTMS). The effect of MPTMS treatment on physical properties is studied through scanning electron microscope (SEM) images, UV-visible transmission, and current-voltage measurements. The SEM images show morphology change of the silver nanofilm, and the UV-visible transmission spectra reveal that the localized surface-plasmon resonance effect is reduced due to the morphology change. These results imply that the uniformity of silver nanofilm is improved by MPTMS treatment for various transparent substrates, resulting in a 100-fold decrease in the electrical resistance of the silver nanofilm.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.11
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• pp.64-74
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• 1999

A new clock skew optimization for clock routing using link-edge insertion is proposed in this paper. It satisfies the given skew bound and prevent the total wire length from increasing. As the clock skew is the major constraint for high speed synchronous ICs, it must be minimized in order to obtain high performance. But clock skew minimization can increase total wire length, therefore clock routing is performed within the given skew bound which can not induce the malfunction. Clock routing under the specified skew bound can decrease total wire length Not only total wire length and delay time minimization algorithm using merging point relocation method but also clock skew reduction algorithm using link-edge insertion technique between two nodes whose delay difference is large is proposed. The proposed algorithm construct a new clock routing topology which is generalized graph model while previous methods uses only tree-structured routing topology. A new cost function is designed in order to select two nodes which constitute link-edge. Using this cost function, delay difference or clock skew is reduced by connecting two nodes whose delay difference is large and distance difference is short. Furthermore, routing topology construction and wire sizing algorithm is developed to reduce clock delay. The proposed algorithm is implemented in C programming language. From the experimental results, we can get the delay reduction under the given skew bound.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.11a
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• pp.11-11
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• 2000

이동통신기술의 급격한 발달로 고주파회로의 packaging과 interconnect 기술의 고성능화 와 저가격화에 대한 새로운 도전이 요구되고 있다‘ 대부분 기존의 무선통신 부품은 P PCB(Printed Wiring Board)기술을 활용하고 있으나 이러한 기술이 점차로 고주파화되는 경 향을 만족시킬수 없어 새로운 고주파 부품기술이 요구되고 있는 실정이다 .. RF 회로를 구성 하기 위하여 PCB소재의 환경적, 치수안정성 문제를 극복하기 위하여 L TCC(Low T Temperature Cofired Ceramics)기술이 최근 주목을 받고 있다. 차세대 이동통신 기술은 수십 GHz 이상의 고주파특성이 우수하고, 고성능의 초소형의 부품을 저가격으로 제조할수 있으며, 시장의 변화에 기민하게 대처할수 있는 기술이 요구되 고 있으며, 이러한 기술적 필요성에 부합할수 있도록 LTCC 기술이 제안되었다. 이러한 C Ceramic Interconnect 기술은 높은 신뢰성을 바탕으로 fine patterning 기술과 저가의 m metallizing 기술로 가능하게 되었다. 초고주파 통신부품기술은 미국과 유럽 등을 중심으로 G GHz 대역또는 mm wave 대역의 기술에 대하여 치열한 기술개발 경쟁을 벌이고 있으며, 이 러한 고주파 패키징 기술을 바탕으로 미래의 군사, 항공, 우주 및 이동통신 기술에 지대한 영향을 미칠수 있는 기반기술로 자리잡을 전망이다. L LTCC 기술은 기존의 후막혼성기술에 비하여 공정이 단순하고 대량생산이 가능하고 가 격이 비교적 저렴하다. 또한 다층구조로 제작할수 있고, 수동소자를 내장할수 있어 회로의 소형화와 고밀도화가 가능하다. 특히 무선으로 초고속 정보를 처리하기 위하여 이동통신기 기의 고주파화가 빠르게 진행됨에 따라서 고분자재료에 비하여 고주파특성이 우수할뿐아니 라 환경적, 치수안정성이 우수한 세라믹소재플 사용함으로써 고주파 손실율을 저감할 수 있 다 .. LTCC 기술은 후막회로 기술과 tape dielectric 기술이 결합된 기술이다. 표준화된 소재 와 공정기술을 활용하여 저가격으로 고성능소자플 제작할 수 있으며, 전극재료로서 높은 전 도도를 갖고 있는 Ag, Cu, Au 및 Pd! Ag릎 사용함으로써 고주파 손실을 저감시킬 수 있다. L LTCC 기술이 최종적으로 소형화, 고기능 고주파 부품기술로 지속적으로 발전하기 위하여 무수축(Zero shrinkage) 소성기술, 광식각 후막기술 등이 원천기술로서 확립될 수 있어야 하 며, 특히 국내의 이동통신 기술에 대한 막대한 투자에도 불구하고 차세대 이동통신 부품기 술에 대한 개발은 상대적으로 미흡한 실정이므로 국내에 LTCC 관련 소재공정 및 부품소자 기술에 대한 개발투자가 시급히 이루워져야 할 것으로 판단된다. 본 발표에서는 지금까지 국내외 LTCC 기술의 발전과정을 정리하였고, 현재 이 기술의 응용과 소재와 공정을 중심으로한 개발현황에 대하여 조사하였으며, 앞으로 LTCC가 발전 해야할 방향을 제시하고자 한다.

• Microbiology and Biotechnology Letters
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• v.42 no.4
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• pp.377-385
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• 2014

In this study, a wastewater treatment system for hypersaline wastewater utilizing the Hypersaline Wastewater Treatment Community (HWTC) has been developed. The hypersaline wastewater treatment efficiency and microbial community of the HWTC were investigated. The average removal efficiencies of chemical oxygen demand were 84% in an HRT of 2.5 days. Microbial community analysis, by denaturing gradient gel electrophoresis (DGGE) of PCR-amplified 16S rRNA gene fragments and 16S rRNA gene clone library, revealed community diversity. The 16S rRNA gene analysis of dominant microbial bacteria in 4% hypersaline wastewater confirmed the presence of Halomonas sp. and Paenibacillus sp. Phylogenetic analysis suggested that the taxonomic affiliation of the dominant species in the HWTC was ${\gamma}$-proteobacteria and firmicutes. These results indicate the possibility that an appropriate hypersaline wastewater treatment system can be designed using acclimated sludge with a halophilic community.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.11
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• pp.9-16
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• 2005

This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.