• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.2
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• pp.267-276
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• 2009

Nowadays, numerous of valuable internet services are available not only for personal computer but also for mobile appliances in wireless network environment. Therefore, as the amount of contents is increased for those services, the storage limitation on mobile devices has became a significant issue. In this paper, we present a new block-level storage network protocol, iATA (Internet Advanced Technology Attachment) as a solution to the above problem. iATA is designed to transport ATA block-level data and command over the ubiquitous TCP/IP network. With iATA, a mobile appliance is able to access and control the ATA storage devices natively through network from anywhere and at anytime as if the storage devices is attached locally. We describe the concepts, design and diverse consideration of iATA protocol. Based on the benchmark experiments and application exploitation, we strongly believe that iATA as a light-weight protocol is efficient and cost-effective to be used as a storage network protocol on a resource limited device that utilizes common-off-the-shelf storage hardware and existing IP infrastructure.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.11
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• pp.1470-1476
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• 2020

This paper describes a design of a lightweight security system-on-chip (SoC) suitable for the implementation of security protocols for IoT and mobile devices. The security SoC using Cortex-M0 as a CPU integrates hardware crypto engines including an elliptic curve cryptography (ECC) core, a SHA3 hash core, an ARIA-AES block cipher core and a true random number generator (TRNG) core. The ECC core was designed to support twenty elliptic curves over both prime field and binary field defined in the SEC2, and was based on a word-based Montgomery multiplier in which the partial product generations/additions and modular reductions are processed in a sub-pipelining manner. The H/W-S/W co-operation for elliptic curve digital signature algorithm (EC-DSA) protocol was demonstrated by implementing the security SoC on a Cyclone-5 FPGA device. The security SoC, synthesized with a 65-nm CMOS cell library, occupies 193,312 gate equivalents (GEs) and 84 kbytes of RAM.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.2
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• pp.149-156
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• 2011

In the recent years, power analysis attacks were widely investigated, and so various countermeasures have been proposed. In the case of block ciphers, masking methods that blind the intermediate values in the en/decryption computations are well-known among these countermeasures. But the cost of non-linear part is extremely high in the masking method of block cipher, and so the countermeasure for S-box must be efficiently constructed in the case of AES, ARIA and SEED. Existing countermeasures for S-box use the masked S-box table to require 256 bytes RAM corresponding to one S-box. But, the usage of the these countermeasures is not adequate in the lightweight security devices having the small size of RAM. In this paper, we propose the new countermeasure not using the masked S-box table to make up for this weak point. Also, the new countermeasure reduces time-complexity as well as the usage of RAM because this does not consume the time for generating masked S-box table.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2021.10a
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• pp.246-248
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• 2021

Recently data has been transformed into a data economy and society that acts as a catalyst for the development of all industries and the creation of new value, and COVID-19 is accelerating digital transformation. In the upcoming intelligent Internet of Things era, the availability of decentralized systems such as blockchain and mixnet is emerging to solve the security problems of centralized systems that makes it difficult to utilize data safely and efficiently. Blockchain manages data in a transparent and decentralized manner and guarantees the reliability and integrity of the data through agreements between participants, but the transparency of the data threatens the privacy of users. On the other hand, mixed net technology for protecting privacy protects privacy in distributed networks, but due to inefficient power consumption efficiency and processing speed issues, low cost, light weight, low power consumption Internet Hard to use. In this paper, we analyze the limitations of conventional mixed-net technology and propose a mixed-net technology method for low power consumption, high speed, and the Internet of things.

• KIPS Transactions on Computer and Communication Systems
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• v.10 no.8
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• pp.223-230
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• 2021

The lightweight block cipher PIPO announced at ICISC'20 has been effectively implemented by applying the bit slice technique. In this paper, we propose a parallel optimal implementation of PIPO for ARM processors. The proposed implementation enables parallel encryption of 8-plaintexts and 16-plaintexts. The implementation targets the A10x fusion processor. On the target processor, the existing reference PIPO code has performance of 34.6 cpb and 44.7 cpb in 64/128 and 64/256 standards. Among the proposed methods, the general implementation has a performance of 12.0 cpb and 15.6 cpb in the 8-plaintexts 64/128 and 64/256 standards, and 6.3 cpb and 8.1 cpb in the 16-plaintexts 64/128 and 64/256 standards. Compared to the existing reference code implementation, the 8-plaintexts parallel implementation for each standard has about 65.3%, 66.4%, and the 16-plaintexts parallel implementation, about 81.8%, and 82.1% better performance. The register minimum alignment implementation shows performance of 8.2 cpb and 10.2 cpb in the 8-plaintexts 64/128 and 64/256 specifications, and 3.9 cpb and 4.8 cpb in the 16-plaintexts 64/128 and 64/256 specifications. Compared to the existing reference code implementation, the 8-plaintexts parallel implementation has improved performance by about 76.3% and 77.2%, and the 16-plaintext parallel implementation is about 88.7% and 89.3% higher for each standard.

• Journal of Digital Contents Society
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• v.13 no.1
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• pp.75-81
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• 2012

SSDs(Solid State Drives) have many attractive features such as high performance, low power consumption, shock resistance, and low weight, so they replace HDDs to a certain extent. An SSD has FTL(Flash Translation Layer) which emulate block storage devices like HDDs. A garbage collection, one of major functions of FTL, effects highly on the performance and the lifetime of SSDs. However, there is no de facto standard for new garbage collection algorithms. To solve this problem, we propose trace driven offline optimal algorithms for garbage collection of FTL. The proposed algorithm always guarantees minimal number of erase operation. In addition, we verify our proposed algorithm using TPC trace.

• Convergence Security Journal
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• v.12 no.1
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• pp.43-48
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• 2012

In this paper, the requirements for information security are presented in the ubiquitous ecological(u-Eco) city. The various definition of ubiquitous city is analyzed first, the concept of the u-Eco City, services and major projects are then presented. The framework of the integrated operating center for u-Eco city is proposed, the privacy, data security and network facility protection in the center are analyzed. Unlike to previously proposed security algorithms, the light-weight encoding algorithms(such as block/stream encoding, pseudo-random generator, hash function, and public key encoding) in the u-Eco city center are required to communicate the information in the ubiquitous sensor network. Furthermore, the principal policies guaranteeing the secrecy and authentication for the private information are also presented.

• Convergence Security Journal
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• v.15 no.2
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• pp.81-89
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• 2015

HIGHT is an 64-bit block cipher, which is suitable for low power and ultra-light implementation that are used in the network that needs the consideration of security aspects. This paper presents a key scheduler that employs the presented LFSR and reverse LFSR that can generate four outputs simultaneously. In addition, we construct new key scheduler that generates 4 subkey bytes at a clock since each round block requires 4 subkey bytes at a time. Thus, the entire HIGHT processor can be controlled by single system clock with regular control mechanism. We synthesize the HIGHT processor using the VHDL. From the synthesis results, the logic size of the presented key scheduler can be reduced as 9% compared to the counterpart that is employed in the conventional HIGHT processor.

• Journal of the Korea Convergence Society
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• v.8 no.11
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• pp.57-62
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• 2017

With various sensors and communications capabilities, the Internet is growing larger as the internet can communicate with the Internet. Given the growing vulnerability of the internet market, the development of security and security is increasing, and the development of the internet is actively evolving and the development of the internet is actively being carried out. In particular, it is required to introduce lightweight and secure authentication schemes, especially those that are difficult to use due to the difficulty of using authentication schemes. Thus, the safety of the secure authentication system of the Internet is becoming very important. Therefore, in this thesis, we propose certification technologies on secure objects to ensure correct, safe communication in the context of the internet context.

• Journal of the Society of Naval Architects of Korea
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• v.51 no.3
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• pp.203-211
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• 2014

To raise the industrial competitiveness in the field of ship-building, it is crucially important that the yard should use production facilities and working space effectively. Among the related works, the management of tremendous blocks' number, the limited area of assembly shops and inefficient personnel and facility management still need to be improved in terms of being exposed to a lot of problems. To settle down these conundrums, the various strategies of block arrangement on the assembly floors have been recently presented and in the results, have increasingly began to be utilized in practice. However, it is a wonder that the sampled or approximated block shapes which usually are standardized projections or the geometrically convex contour only have been prevailed until now. In this study, all parts including the panel, stiffeners, outer shells, and all kinds of outfitting equipment are first extracted using the Volume Primitive plug-in module from the ship customized CAD system and then, the presented system constructs a simpler and more compact ship data structure and finally generates the novel projected contours for the block arrangement system using the adaptive concave hull algorithm.