• Journal of IKEEE
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• v.3 no.1 s.4
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• pp.118-125
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• 1999

A capacitance method to extract the metallurgical channel length of LDD MOSFET's, which is defined by the length between the metallurgical junction of substrate and source/drain under the gate, is presented. The gate capacitances of the finger type and plate type LDD MOSFET gate test patterns with same total gate area are measured. The gate bias of each pattern is changed, and the capacitances are measured with source, drain, and substrate bias grounded. The differences between two test pattern's capacitance data are plotted. The metallurgical channel length is extracted from the peak data at a maximum point using a simple formula. The numerical simulation using two-dimensional device simulator is performed to verify the proposed method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.1-7
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• 2008

In this work, a two dimensional, self-consistent Poisson-$Schr{\ddot{o}}dinger$ solver has been implemented to study C-V characteristics in nanometer scale MuGFETs with considering quantum effects. The quantum-mechanical effects on gate-channel capacitance for different device dimension and gate configurations of nanometer scale MuGFETs have been analyzed. It has been found that 4he gate-channel capacitance per unit gate area is increased as the device dimension decreases. For different gate configurations, the gate-channel capacitance is decreased with increase of effective gate number. Those resu1ts have been explained by the distribution profile of electron concentration in the silicon surface and inversion capacitance. The length of inversion-layer centroid has been calculated from inversion capacitance with device dimension and gate configurations.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.17 no.6
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• pp.83-88
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• 2003

This paper analyses a fault operation due to the effect of miller capacitance, which severely influences the performance of the IPMs based on computer-aided simulations, and also it presents a good solution to solve that problem. A miller capacitance existed between gate and collect is very closely related to the stray capacitance formed between gate and emitter, and the value of gate resistor. These relationships are proved by the computer-aided simulation. Based on the PSpice simulation results, a customized IPM employing an auxiliary circuit is presented to minimize a fault operation. And it is compared to the standard IPM by the experimental waveform. As a result, it is verified that a customized IPM has a voltage margin to prevent a fault operation approx. 3 [V].

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.59-68
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• 1999

The timing characteristics of an ASIC are analyzed based on the propagation delays of each gate and interconnect wire. The gate delay can be modeled using the two-dimensional delay table whose index variables are the input transition time and the output load capacitance. The AWE technique can be adopted as an algorithm to compute the interconnect delay. Since these delays are affected by the interaction to the two-dimensional delay table and the AWE technique. A method to model this effect has been proposed through the effective capacitance and the gate driver model under the assumption of single driving gate. This paper presents a new technique to handle the multiple CMOS gates driving interconnect wire by extending previous approach. This technique has been implemented in C language and applied to several interconnect circuits driven by multiple CMOS gates. In most cases, we found a few tens of speed-up and only a few percents of errors in computing both of gate and interconnect delays, compared to SPICE.

• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.271-273
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• 2020

SiC 기반의 전력용 반도체 소자들은 스위칭 속도가 빠르고 높은 차단 전압을 가져 dv/dt가 크다. 중전압 이상에서 게이트 드라이버에 절연된 전원 공급을 하기 위해 소형 변압기가 사용된다. 하지만 변압기의 1, 2 차 권선 사이에 수십 pF 이상의 기생 커패시턴스가 존재하며, 높은 전압을 고속으로 스위칭 하게 될 경우 기생 커패시턴스를 통해 제어부로 공통 모드 전류가 흘러 오작동을 야기할 수 있다. 본 연구에서는 변압기를 대체하여 무선전력전송 코일을 이용한 게이트 드라이버용 절연된 전원공급 장치를 제안한다. 무선전력전송 코일 사이의 거리를 수 mm 이상 이격시켜 코일 사이의 기생 커패시턴스를 1 pF 이하로 줄이고 높은 절연 특성을 가질 수 있다. 무선전력 전송의 공진 토폴로지는 직렬-병렬을 선택했고, 2 MHz에서 높은 효율을 갖도록 I-core 코일을 2.2cm × 1.5cm × 1.7cm으로 제작해 검증했다.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.8
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• pp.853-859
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• 2014

This study presents a technique for extracting all the extrinsic parameters of HEMTs by minimizing the residual errors between a pinch-off cold-FET's gate and drain pad de-embedded Z-parameters and its modeled Z-parameters calculated by the cold-FET's remaining parameters. The presented technique allows us to successfully extract the remaining extrinsic parameter values as well as the gate and drain pad capacitance value without the additional fabrications of the gate and drain dummy pad.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.11
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• pp.932-939
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• 2000

본 논문은 정적 CMOS 회로의 단락 전류로 인한 전력소모와 게이트의 전달 지연시간을 구하기 위한 간단한 방법을 제시한다. 단락전류식은 게이트와 드레인 사이에 존재하는 커플링 커패시턴스의 영사한 후 모형화한 전류 수식을 기반으로 CMOS 회로의 지연 시간을 예측하기 위한 거시모형과 수식들을 제안하였다. 제안된 방법은 시뮬레이션을 통하여 현재의 기술 동향 특성인 신호 천이시간과 부하 커패시턴스가 감소하는 경우에 대해 이전의 연구보다 더욱 정확하고 신속히 예측할 수 있음을 보였다. 또한 제안된 거시 모형은 전류식이 변할지라도 전력소모와 타이밍 수준에서의 지연시간을 계산하는데 쉽게 적용이 가능하다.

• Journal of IKEEE
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• v.22 no.1
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• pp.209-212
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• 2018

In this work, we developed P(VDF-TrFE) organic/ferroelectric material based metal-ferroelectric-metal (MFM) capacitors in order to improve the switching characteristics of gallium nitride (GaN) heterojunction field-effect transistors (HFET). The 27 nm-thick P(VDF-TrFE) MFM capacitors exhibited about 60 ~ 96 pF capacitance with a polarization density of $6{\mu}C/cm^2$ at 4 MV/cm. When the MFM capacitor was connected in series with the gate electrode of GaN HFET, the subthreshold slope decreased from 104 to 82 mV/dec.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.39-46
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• 2009

A fast-switching current-pulse driver for light emitting diode (LED) backlight is proposed. It uses a regulated drain current mirror (RD-CM) [1] and a high-voltage NMOS transistor (HV-NMOS). It achieves the fast-response current-pulse switching by using a dynamic gain-boosting amplifier (DGB-AMP). The DGB-AMP does not discharge the large HV-NMOS gate capacitance of the RD-CM when the output current switch turns off. Therefore, it does not need to charge the HV-NMOS gate capacitance when the switch turns on. The proposed current-pulse driver achieves the fast current switching by removing the repetitive gate discharging and charging. Simulation results were verified with measurements performed on a fabricated chip using a 5V/40V 0.5um BCD process. It reduces the switching delay to 360ns from 700ns of the conventional current-pulse driver.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.12
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• pp.10-16
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• 2003

To analyze the effects of the air-bridge parasitic capacitances on the performance of coplanar waveguide pseudomorphic high electron mobility transistors (CPW PHEMTs), the gate-to-air-bridge ( $C_{ag}$ ) and the drain-to air-bridge ( $C_{ad}$ ) capacitances were taken into account plus the conventional pinched-off cold. FET circuit model. To examine the effects of the parasitic capacitances due to the air-bridges, a variety routing schemes for the air-bridge interconnection were adopted for fabricating the 0.1-${\mu}{\textrm}{m}$ $\Gamma$-gate length CPW HEMT's. According to air-bridge schemes, the $S_{21}$ gain is affected considerably. From the results of the fabricated CPW PHEMT, the $C_{ag}$ and $C_{ad}$ is one of the important factor of decreasing the gain of HEMTs.