• Journal of IKEEE
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• v.26 no.2
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• pp.313-318
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• 2022

The feedback voltage detection structure is proposed to alleviate overshoot and undershoot caused by the removal of the existing external output capacitor. Conventional LDO regulators suffer from overshoot and undershoot caused by imbalances in the power supply voltage. Therefore, the proposed LDO is designed to have a more improved transient response to form a new control path while maintaining only the feedback path of the conventional LDO regulator. A new control path detects overshoot and undershoot events in the output stage. Accordingly, the operation speed of the pass element is improved by charging and discharging the current of the gate node of the pass element. LDO regulators with feedback voltage sensing architecture operate over an input voltage range of 3.3V to 4.5V and have a load current of up to 200mA at an output voltage of 3V. According to the simulation result, when the load current is 200mA, it is 73mV under the undershoot condition and 61mV under the overshoot condition.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.21 no.7
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• pp.84-90
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• 2022

The purpose of the cover housing component of a car door is to protect the terminals of the plug housing that connects the electric control unit on the door side to the car body. Therefore, for a smooth assembly with the plug housing and to prevent contaminants from penetrating into the gaps that occur after assembly, the warpage of the cover housing should be minimized. In this study, to minimize the warpage of the cover housing, optimization was performed for design factors related to the mold and processes based on the injection molding simulation. These design factors include gate location, gate diameter, injection time, resin temperature, mold temperature, and packing pressure. To optimize the design factors, Taguchi's approach to the design of experiments was adopted. The optimal combination of the design factors and levels that minimize warpage was predicted through L₁₈-orthogonal array experiments and main effects analysis. Moreover, the warpage under the optimal design was estimated by the additive model, and it was confirmed through the simulation experiment that the estimated result was quite consistent with the experimental result. Additionally, it was found that the warpage under the optimal design was significantly improved compared to both the warpage under the initial design and the best warpage among the orthogonal array experimental results, which numerically decreased by 36.9% and 23.4%, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.8
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• pp.39-48
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• 2016

In this paper, we propose thermal resistance compact model of FinFET structure that has hexagon shaped source/drain. The heating effect and thermal properties were increased by reduced size of the device, and thermal resistance is an important factor to analyze the effect and the properties. The heat source and each contact that is moved heat out were set up in transistor, and domain is divided by the heat source and the four parts of contacts : source, drain, gate, substrate. Each contact thermal resistance model is subdivided as a easily interpretable structure by analyzing the temperature and heat flow of the TCAD simulation results. The domains are modeled based on an integration or conformal mapping method through the structure parameters according to its structure. First modeled by analyzing the thermal resistance to a single fin, and applying the change in the parameter of the channel increases to improve the accuracy of the thermal resistance model of the multi-fin/ finger. The proposed thermal resistance model was compared to the thermal resistance by analyzing results of the 3D Technology CAD simulations, and the proposed total thermal resistance model has an error of 3 % less in single and multi-finl. The proposed thermal resistance model can predict the thermal resistance due to the increase of the fin / finger, and the circuit characteristics can be improved by calculating the self-heating effect and thermal characterization.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.4
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• pp.78-86
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• 1999

In this paper, a distributed arithmetic digital neural network with learning and testing phase implemented in a body has been studied. The proposed technique is based on the two facts; one is that the weighting coefficients adjusted will be stored in registers without shift, because input values or input patterns are not changed while learning and the other is that the input patterns stored in registers are not changed while testing. The proposed digital neural network is simulated by hardware description language such as VHDL and verified the performance that the neural network was applied to the recognition of seven-segment. To verify proposed neural networks, we compared the learning process of modified perceptron learning algorithm simulated by software with VHDL for 7-segment number recognizer. The results are as follows: There was a little difference in learning time and iteration numbers according to the input pattern, but generally the iteration numbers are 1000 to 10000 and the learning time is 4 to 200$\mu\textrm{s}$. So we knew that the operation of the neural network is learned in the same way with the learning of software simulation, and the proposed neural networks are properly operated. And also the implemented neural network can be built with less amounts of components compared with board system neural network.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.28 no.5B
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• pp.575-589
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• 2008

In the present work, we investigate the hydrodynamic behavior of a turbulent bore, such as tsunami bore and tidal bore, generated by the removal of a gate with water impounded on one side. The bore generation system is similar to that used in a general dam-break problem. In order to the numerical simulation of the formation and propagation of a bore, we consider the incompressible flows of two immiscible fluids, liquid and gas, governed by the Navier-Stokes equations. The interface tracking between two fluids is achieved by the volume-of-fluid (VOF) technique and the M-type cubic interpolated propagation (MCIP) scheme is used to solve the Navier-Stokes equations. The MCIP method is a low diffusive and stable scheme and is generally extended the original one-dimensional CIP to higher dimensions, using a fractional step technique. Further, large eddy simulation (LES) closure scheme, a cost-effective approach to turbulence simulation, is used to predict the evolution of quantities associated with turbulence. In order to verify the applicability of the developed numerical model to the bore simulation, laboratory experiments are performed in a wave tank. Comparisons are made between the numerical results by the present model and the experimental data and good agreement is achieved.

• The KIPS Transactions:PartC
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• v.10C no.3
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• pp.377-386
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• 2003

This study suggested a technique to maintain an efficient core-based multicast tree using weighted clustering factors in mobile Ad-hoc networks. The biggest problem with the core-based multicast tree routing is to decide the position of core node. The distance of data transmission varies depending on the position of core node. The overhead's effect on the entire network is great according to the recomposition of the multicast tree due to the movement of core node, clustering is used. A core node from cluster head nodes on the multicast tree within core area whose weighted factor is the least is chosen as the head core node. Way that compose multicast tree by weighted clustering factors thus and propose keeping could know that transmission distance and control overhead according to position andmobility of core node improve than existent multicast way, and when select core node, mobility is less, and is near in center of network multicast tree could verification by simulation stabilizing that transmission distance is short.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.1-8
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• 2011

One of the most important parameters that limit maximum output power of transistor is breakdown. InAlAs/InGaAs/GaAs Metamorphic HEMTs (MHEMTs) have some advantages, especially for cost, compared with InP-based ones. However, GaAs-based MHEMTs and InP-based HEMTs are limited by lower breakdown voltage for output power even though they have good microwave and millimeter-wave frequency performance with lower minimum noise figure. In this paper, InAlAs/$In_xGa_{1-x}As$/GaAs MHEMTs are simulated and analyzed for breakdown. The parameters affecting breakdown are investigated in the fabricated 0.1-${\mu}m$ ${\Gamma}$-gate MHEMT device having the modulation-doped $In_{0.52}Al_{0.48}As/In_{0.53}Ga_{0.47}As$ heterostructure on the GaAs wafer using the hydrodynamic transport model of a 2D commercial device simulator. The impact ionization and gate field effect in the fabricated device including deep-level traps are analyzed for breakdown. In addition, Indium mole-fraction-dependent impact ionization rates are proposed empirically for $In_{0.52}Al_{0.48}As/In_xGa_{1-x}As$/GaAs MHEMTs.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.145-155
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• 2013

In this paper, we proposed a $4{\times}4$ block parallel architecture of interpolation for high-performance H.264/AVC Fractional Motion Estimation in 8K UHD($7680{\times}4320$) video real time processing. To improve throughput, we design $4{\times}4$ block parallel interpolation. For supplying the $10{\times}10$ reference data for interpolation, we design 2D cache buffer which consists of the $10{\times}10$ memory arrays. We minimize redundant storage of the reference pixel by applying the Search Area Stripe Reuse scheme(SASR), and implement high-speed plane interpolator with 3-stage pipeline(Horizontal Vertical 1/2 interpolation, Diagonal 1/2 interpolation, 1/4 interpolation). The proposed architecture was simulated in 0.13um standard cell library. The gate count is 436.5Kgates. The proposed H.264/AVC Fractional Motion Estimation can support 8K UHD at 30 frames per second by running at 187MHz.

• Journal of Broadcast Engineering
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• v.17 no.2
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• pp.374-387
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• 2012

In this paper, we implement a new hardware for finding the significant coefficients of a digital hologram and ciphering them using discrete wavelet packet transform (DWPT). Discrete wavelet transform (DWT) and packetization of subbands is used, and the adopted ciphering technique can encrypt the subbands with various robustness based on the level of the wavelet transform and the threshold of subband energy. The hologram encryption consists of two parts; the first is to process DWPT, and the second is to encrypt the coefficients. We propose a lifting based hardware architecture for fast DWPT and block ciphering system with multi-mode for the various types of encryption. The unit cell which calculates the repeated arithmetic with the same structure is proposed and then it is expanded to the lifting kernel hardware. The block ciphering system is configured with three block cipher, AES, SEED and 3DES and encrypt and decrypt data with minimal latency time(minimum 128 clocks, maximum 256 clock) in real time. The information of a digital hologram can be hided by encrypting 0.032% data of all. The implemented hardware used about 200K gates in $0.25{\mu}m$ CMOS library and was stably operated with 165MHz clock frequency in timing simulation.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.4
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• pp.421-426
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• 2010

Due to the ease of deployment and the extended coverage, wireless mesh networks (WMNs) are gaining popularity and research focus. For example, the routing protocols that enhance the throughput on the WMNs and the link quality measurement schemes are among the popular research topics. However, most of these works assume that the locations of the mesh routers are predetermined. Since the operators in an Indoor mesh network can determine the locations of the mesh routers by themselves, it is essential to the WMN performance for the mesh routers to be initially placed by considering the performance issues. In this paper, we propose a mesh router placement scheme based on genetic algorithms by considering the characteristics of WMNs such as interference and topology. There have been many related works that solve similar problems such as base station placement in cellular networks and gateway node selection in WMNs. However, none of them actually considers the interference to the mesh clients from non-associated mesh routers in determining the locations of the mesh routers. By simulations, we show that the proposed scheme improves the performance by 30-40% compared to the random selection scheme.