• Journal of IKEEE
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• v.12 no.2
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• pp.110-117
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• 2008

This paper presents a new Insulated Gate Bipolar Transistor(IGBT) based on Non Punch Through(NPT) IGBT structure for power switching device. The proposed structure has adding N+ beside the P-base region of the conventional IGBT structure. The added n+ diffusion of the proposed device ensure device has faster turn-off time and lower forward conduction loss than the conventional IGBT structure. But, added n+ region can reduce th breakdown voltage and latching current density of the proposed device due to its high doping concentration. This problems can be overcome by using diverter on the right side of the device. In the simulation results, turn-off time of the proposed device is 0.3us and the on-state voltage drop is 3V. The results show that the proposed device has superior characteristic than conventional structure.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.9B
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• pp.823-833
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• 2003

To satisfy the requirements of the real-time Internet services, queue management and scheduling schemes should be enhanced to accommodate the delay and jitter characteristic of them. Although the existing queue management schemes can address the congestion problems of TCP flows, they have some problems in supporting real-time services. That is, they show performance degradation when burst traffics are continuously going into the system after the queue is occupied at a predefined threshold level. In addition, under the congestion state, they show large jitter, which is not a desirable phenomenon for real-time transmissions. To resolve these problems, we propose a SDRED (State Dependent Random Early Detection) and dynamic scheduling scheme that can improve delay and jitter performances by adjusting RED parameters such as ma $x_{th}$ and $w_{q}$ according to the queue status. The SDRED is designed to adapt to the current traffic situation by adjusting the max,$_{th}$ and $w_{q}$ to four different levels. From the simulation results, we show that the SDRED decreases packet delays in a queue and has more stable jitter characteristics than the existing RED, BLUE, ARED and DSRED schemes.mes.mes.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.681-684
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• 2011

In this paper, the relationship of potential and charge distribution in channel for double gate(DG) MOSFET has been derived from Poisson's equation using Gaussian function. The subthreshold swing has been investigated according to projected range and standard projected deviation, variables of Gaussian function. The analytical potential distribution model has been derived from Poisson's equation, and subthreshold swing has been obtained from this model. The subthreshold swing has been defined as the derivative of gate voltage to drain current and is theoretically minimum of 60mS/dec, and very important factor in digital application. Those results of this potential model are compared with those of numerical simulation to verify this model. As a result, since potential model presented in this paper is good agreement with numerical model, the subthreshold swings have been analyzed according to the shape of Gaussian function.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.6
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• pp.1460-1464
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• 2010

In the paper, the breakdown voltage of Trench D-MOSFET have been analyzed by using MircoTec. The technology for characteristic analysis of device for high integration is changing rapidly. Therefore to understand characteristics of high-integrated device by computer simulation and fabricate the device having such characteristics became one of very important subjects. A Trench MOSFET is the most preferred power device for high voltage power applications. The oxide thickness and doping concentration in Trench MOSFET determines breakdown voltage and extensively influences on high voltage. We have investigated the breakdown voltage characteristics according to variation of doping concentration from $10^{15}cm^{-3}$ to $10^{17}cm^{-3}$ in this study. We have also investigated the breakdown voltage characteristics according to variation of oxide thickness and junction depth.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.3C
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• pp.281-292
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• 2008

A main application of sensor networks are to monitor and to send information about a possibly hostile environment to a powerful base station connected to a wired network. To conserve power from each sensor, intermediate network nodes should aggregate results from individual sensors. However, it can make it that a single compromised sensor can render the network useless, or worse, mislead the operator into trusting a false reading. In this paper, we propose a protocol to give us a key aggregation mechanism that intermediate network nodes could aggregate data more safely. The proposed protocol is more helpful at multi-tier network architecture in secure sessions established between sensor nodes and gateways. From simulation study, we compare the amount of the energy consumption overhead, the time of key transmission and the ratio of of key process between the proposed method and LHA-SP. The simulation result of proposed protocol is low 3.5% a lord of energy consumption than LHA-SP, the time of key transmission and the ration of key process is get improved result of each 0.3% and 0.6% than LHA-SP.

• Journal of IKEEE
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• v.22 no.2
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• pp.420-426
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• 2018

In the near future, CNTFET(Carbon NanoTube Field Effect Transistor) is considered as one of the most promising candidate for the replacement of modern silicon-based transistors by utilizing the ballistic or near-ballistic transport capability of CNT(Carbon NanoTube). For the large-scale fabrication of high performance CNTFET, semiconducting CNTs have to be well-aligned with a fixed pitch and high densities in the each CNTFET. However, due to the immaturity of the CNTFET fabrication process, CNTs can be unevenly positioned in a CNTFET and existing HSPICE library file cannot support the circuit level evaluation of performance variation caused by the unevenly positioned CNTs. To evaluate the performance variation, linear programming methodology was suggested previously, but the errors can be made during the calculation of the current and the gate capacitance of a CNTFET. In this paper, the reasons causing errors will be discussed in detail and the new methodology to reduce the errors will be also suggested. Simulation results shows that the errors can be reduced from 7.096% to 3.15%.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.66-76
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• 1998

In this paper, we implement a buffer capable of handling short loops references to statistically lower the miss rate of variable-length instructions stored in the instruction buffer. MAU(Mark Appending Unit) takes the instructions as they are fetched from external memory, performs some initial decode operations and stores the results of the decode in the buffer for reducing multiple decodes when instructions are executed repeatedly such as in a loop. It includes a decision block of whether hit or not for effectively processing branch instructions Each module of the proposed architecture of processing variable-length instruction is described in VHDL structurally and behaviorally and whether it is working well or not is checked on V-System simulator of Model Technology Inc. We synthesized and simulated the architecture using an ASIC Synthesizer tool with 0.6$\mu\textrm{m}$ 5-Volt CMOS COMPASS library. Operation speed is up to 140MHz. The architecture includes about 17,000 gates.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.11
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• pp.74-84
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• 2000

This paper deals with procedures for design and implementation of a DSP, which is compatible with TMS320C30 DSP. CBS(Cycle Based Simulator) is developed to study the architecture of the target DSP. The simulator gives us detailed information such as function block operation, control signal values, register condition, bus and memory values when a instruction is being carried out. RTL design is carried out by VHDL. Logic simulation and hardware emulation are employed to verify proper operation of the design. The DSP is fabricated with 0.6${\mu}m$ CMOS technology. The Chip has 450,000 gates complexity, $9{\times}9mm^2$ area, 20 MIPS operation speed. It is confirmed by running 109 instructions out of 114 instructions and 13 kinds of algorithm that the developed DSP has compatibility with TMS320C30.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.3
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• pp.8-16
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• 1999

This paper describes a VLSI design of Reed-Solomon(RS) decoder using the modified Euclid algorithm, with the main theme focused on the $\textit{GF}(2^8)$. To get area-efficient design, a number of new architectures have been devised with maximal register and Euclidean ALU unit sharing. One ALU is shared to replace 18 ALUs which computes an error locator polynomial and an error evaluation polynomial. Also, 18 registers are shared to replace 24 registers which stores coefficients of those polynomials. The validity and efficiency of the proposed architecture have been verified by simulation and by FLEX$^TM$ FPGA implementation in hardware description language VHDL. The proposed Reed-Solomon decoder, which has the capability of decoding RS(208,192,17) and RS(182,172,11) for Digital Versatile Disc(DVD), has been designed by using O.6$\mu\textrm{m}$ CMOS TLM Compass$^TM$ technology library, which contains totally 17k gates with a core area of 2.299$\times$2.284 (5.25$\textrm{mm}^2$). The chip can run at 20MHz while the DVD requirement is 3.74MHz.

• Journal of Korea Society of Industrial Information Systems
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• v.13 no.4
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• pp.73-82
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• 2008

Collecting and managing the sensor information through the Internet is critical to effectively manage and utilize the sensor information. The interworking technique of the sensor network and internet is required to realize the desirable condition for managing and utilizing the sensor information. Among many interworking techniques, the translation technique using the gateway had been widely studied. However, the technique which mounts IP-based Internet protocols directly on the sensor node is getting more attention recently. Particularly, IPv6 is suitable for the communication protocol for the sensor network, because its features, such as abundant address space or address auto-configuration, are well matched with the sensor network. In this paper, we design the tiny UDP/IPv6 protocol functions which are suitable for the sensor network environment, and we implemented the functions with TinyOS based nesC. After we examined the simulation results of by using TOSSIM and TinyViz, we carried out the experimental performance evaluation for the program by mounting the tiny UDP/IPv6 on the sensor node (Mote).