• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.13-18
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• 2007

This paper presents the experimental findings on the different degradation mechanism which depends on the gate oxide thickness in lateral DMOS transistors. For thin oxide devices, the generation of interface states in the channel region and the trapped holes in the drift region is found to be the causes of the device degradation. For thick devices, the generation of interface states in the channel region is found to be the causes of the device degradation. We confirmed the different degradation mechanism using device simulation. From the comparison of device degradation under DC and AC stress, it is found that the device degradation is more significant under DC stress than one under AC stress. The device degradation under AC stress is more significant in high frequency. Therefore the hot carrier induced degradation should be more carefully considered in the design of RF LDMOS transistors and circuit design.

• Journal of the Korean Society for Railway
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• v.13 no.5
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• pp.504-508
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• 2010

The development of high voltage Insulated Gate Bipolar Transistor (IGBT) have given new device advantage in the areas where they compete with conventional GTO (Gate Turnoff Thyristor) technology. The IGBT combines the advantages of a power MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) and a bipolar power transistor. The change of electrical characteristics for IGBT is mainly coming from the change of characteristics of MOSFET at the input gate and the PNP transistors at the output. The change of threshold voltage, which is one of the important design parameters, is brought by charge trapping at the gate oxide under the environment that radiation exists. The energy loss will be also studied as the inductance values are changed. In this paper, the electrical characteristics are simulated by SPICE, and compared for variation of inductance and threshold voltage based on IGBT.

• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.72-79
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• 2003

Classical designs of optical transimpedance preamplifier for p-i-n photodiode receiver circuits generally employ common source transimpedance input stages. In this paper, we explore the design of a class of current-mode optical transimpedance preamplifier based upon common gate input stages. A feature of current-mode optical transimpedance preamplifier is high gain and high bandwidth. The bandwidth of the transimpedance preamplifier can also be increased by the capacitive peaking technique. In this paper we included the development and application of a circuit analysis technique based on the minimum noise. We develop a general formulation of the technique, illustrate its use on a number of circuit examples, and apply it to the design and optimization of the low-noise transimpedance amplifier. Using the noise minimization method and the capacitive peaking technique we designed a transimpedance preamplifier with low noise, high-speed current-mode transimpedance preamplifier with a 1.57GHz bandwidth, and a 2.34K transimpedance gain, a 470nA input noise current. The proposed preamplifier consumes 16.84mW from a 3.3V power supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.10
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• pp.2217-2222
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• 2011

In this paper, the relationship of potential and charge distribution in channel for double gate(DG) MOSFET has been derived from Poisson's equation using Gaussian function. The relationship of subthreshold swing and oxide thickness has been investigated according to variables of doping distribution using Gaussian function, i.e. projected range and standard projected deviation, The analytical potential distribution model has been derived from Poisson's equation, and subthreshold swing has been obtained from this model for the change of oxide thickness. The subthreshold swing has been defined as the derivative of gate voltage to drain current and is theoretically minimum of 60 mS/dec, and very important factor in digital application. Those results of this potential model are compared with those of numerical simulation to verify this model. As a result, since potential model presented in this paper is good agreement with numerical model, the relationship of subthreshold swing and oxide thickness have been analyzed according to the shape of doping distribution.

• Journal of Broadcast Engineering
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• v.10 no.2
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• pp.182-189
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• 2005

In this paper, an asymmetric WDM-EPON transmission scheme is proposed to be used in a high speed access network system, which is required to implement the convergence of broadcast and communication. WDM is used for downstream transmission from OLT to access nodes, satisfying wide bandwidth requirement for broadcasting and various multimedia services. And an EPON scheme, which is cheaper than WDM, is applied to upstream transmission where less bandwidth is required. A transmission test in physical layer was performed successfully and the results are provided. If ONUs are to be used in a home gateway, its protocol should be appropriate to its traffic pattern. Voice is sensitive to a time delay while data is not. A new dynamic bandwidth assignment protocol for PON system, which can cope with various types of data in access network is proposed and its performance is analysed. A maximum cycle time is specified to achieve the QoS of signals sensitive to time delay. And a minimum window is specified to prevent the downstream control signals from uprising. It is shown by simulation that the proposed EPON protocol can provide a better performance than previous ones.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.13-22
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• 2010

Independent-Gate-Mode Double-Gate(IGM-DG) MOSFET overcomes the limitation of bulk-MOSFET's channel controllability and enables to control the front and back-gate voltages independently. Therefore, circuit designs utilizing the IGM-DG MOSFETs provide the advantage of setting 4-terminal freely, hence achieving not only the performance improvement but also the larger scale integration. This paper presents a 15Gb/s optical receiver with a 1.0V power supply voltage, which consists of a transimpedance amplifier (TIA), a feedforward limiting amplifier (LA), and an output buffer. HSPICE simulations were conducted to confirm the circuit performance, and also to verify the circuit stability issues which may occur from the variations of process and supply voltage.

• Journal of IKEEE
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• v.24 no.1
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• pp.364-367
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• 2020

This paper presents the off-grid PV-ESS system of sequential voltage control method applied to OR logic gate. The conventional off-grid PV-ESS system with the low-voltage series connection has problems due to capacity expansion. To solve these problems, this paper proposes a noble PV-ESS system with high efficiency and low cost by applying sequential voltage control technique of the high-voltage series connection of analog circuit type. The input voltage of DC to AC inverter can be converted from the low-voltage by the combinations of series connection of the conventional cascaded 24V solar cell unit modules to the high-voltage of 384V in battery. The output voltage of the battery was 384V as the each input voltage of three phase DC to AC inverter, and the each output voltage of three phase 10kW DC to AC inverter is designed to be AC380V@60Hz as the line to line rms voltage value. To prove the validity of the theoretical analysis by PSIM simulation, the operating characteristics of sequential voltage control system with OR logic gate were confirmed through experiment results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.9
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• pp.1627-1634
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• 2017

In this work, a junctionless transistor with different film thickness of amorphous InGaZnO has been fabricated and it's instability has been analyzed with different film thickness under positive and negative gate stress as well as light illumination. It was found that the threshold voltage shift and the variation of drain current have been increased with decrease of film thickness under the condition of gate stress and light illumination. The reasons for the observed results have been explained by stretched-exponential model and device simulation. Due to the reduced carrier trapping time with decrease of film thickness, electrons and holes can be activated easily. Due to the increase of vertical channel electric field reaching the back interface with decrease of film thickness, more electrons and holes can be accumulated in back interface. When one decides the film thickness for the fabrication of junctionless transistor, the more significant device instability with decrease of film thickness should be consdered.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.15-30
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• 2004

In this paper, an analytical modeling for the dark and photo-current characteristics of a buried-gate short- channel GaAs MESFET is presented. The presented model shows that the increase of drain current under illumination is largely due to not the increase of photo-conductivity in the neutral region but the narrowing effect of the depletion layer width. The carrier density profile within the neutral region is derived from solving the carrier continuity equation one-dimensionally. In deriving the photo-generated current, we assume that the photo-current is compensated with the thermionic emission current at the gate-channel interface. Moreover, the two-dimensional Poisson's equation is solved by taking into account the drain-induced longitudinal field effect. In conclusion, the proposed model seems to provide a reasonable explanation for the dark and photo current characteristics in a unified manner.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2018.05a
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• pp.57-58
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• 2018

As interest in the Internet of Things increases, technologies are being studied to handle information exchanged between things using the Internet of Things. Specially, as container terminals are automated, the use of the Internet of Things in the terminals increases and varies. However, the use of the Internet of Things to enhance the efficiency of the container terminal operation is insufficient. Currently, the container terminal shows that the arrival pattern of the external truck is concentrated at a particular time. This resuls in gate congestion and affects the waiting times of the truck. The damage is caused by environmental pollution problems and social problems in neighboring port areas. Therefore, in this thesis, we will analyze the causes of the external truck's waiting time problems affecting the gate congestion at container terminals and study methods to mitigate congestion under Internet of Things environment.