• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.7
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• pp.34-41
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• 1999

In this paper, hot carrier induced performance degradation of peripheral circuits in memory devices such as static type imput buffer, latch type imput buffer and sense amplifier circuit has been measured and analyzed. The used design and fabrication of the peripheral circuits were $0.8 {\mu}m$ standard CMOS process. The analysis method is to find out which device is most significantly degraded in test circuits by using spice simulation, and then to characterize the correlation between device and circuit performance degradation. From the result of the performance degradation of static type input buffer, the trip point was increased due to the transconductance degradation of NMOS. In the case of latch type input buffer, there was a time delay due to the transconductance degradation of NMOS device. Finally, hot carrier induced the decrease of half-Vcc voltage and the increased of sensing voltage in sense amplifier circuits have been measured.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.3
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• pp.185-191
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• 2018

In this paper, an improved Norton amplifier is proposed and the problems caused by the current input in the Norton amplifier, which has advantages in current transmission, are analyzed. The output of the voltage follower consisting of an operational-amplifier with constant output voltage characteristics is used as an input terminal of the proposed circuit. It is configured to detect the power supply current passing through the voltage follower and extract the current from the input terminal. The performance of the improved Norton amplifier is verified at experiment according to the input current. The results are compared with conventional Norton amplifier. Consequently, the input offset voltage, which is a problem in the conventional Norton amplifier, was removed in the proposed circuit. In addition, the average error of the output voltage with respect to the input current was reduced to 4.755%. It is verified that the characteristics of the proposed circuit are improved.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.1
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• pp.53-60
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• 2010

This paper presents a novel gain control system composed of a feedback circuit, Two stage Low Noise Amplifier (LNA) using 0.18 um CMOS technology for 5.2 GHz. The feedback circuit consists of the seven function blocks: peak detector, comparator, ADC, IVE(Initial Voltage Elimination) circuit, switch, storage, and current controller. We focus on detecting signal and designing storage circuit that store the previous state. The power consumption of the feedback circuit in the system can be reduced without sacrificing the gain by inserting the storage circuit. The adaptive front-end system with the feedback circuit exhibits 11.39~22.74 dB gain, and has excellent noise performance at high gain mode. Variable gain LNA consumes 5.68~6.75 mW from a 1.8 V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.7
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• pp.493-502
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• 2001

This paper propose a new built-in current sensor(BICS) for current testing that has some advantages compared with conventional logic testing. The designed BICS detects the fault in circuit under test (CUT) and makes a Pass/Fail signal by comparison between CUT current and duplicated inverter current. The proposed circuit consists of a differential amplifier, a comparator and a inverter. It requires 10 MOSFETs and 3 inverters. Since the designed BICS do not require the extra clock, the added extra pin is only one output pin. The mode selection is not used in this circuit. Therefore we can apply the circuit to on-line testing. The validity and effectiveness are verified through the HSPICE simulation of circuits with defects. When CUT is a 8$\times$8 parallel multiplier, area overhead of the BICS is about 4.34%.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2859-2862
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• 2003

본 논문에서는 과전류로부터 보호해야 할 트랜지스터의 정격전력을 고려해 protection level 을 결정하는 과 전류 보호회로를 제안하였다. 기존의 과전류 보호회로는 과부하시 출력 트랜지스터 양단 전압과는 무관하게 단순히 전류의 크기만을 감지해 보호회로를 동작시키기 때문에 출력 트랜지스터의 정격전력을 고려하지 않고 동작을 한다. 하지만 제안된 회로는 출력전압과 출력전류의 크기를 모두 감지해 protection 여부를 결정하기 때문에 protection 시 출력 트랜지스터에서의 소모전력이 거의 일정하도록 유지시켜준다. Protection level 설정에 있어서 기존 방식과 다른 점을 먼저 살펴보고, 실제 오디오 증폭기의 보호회로로 사용된 회로의 동작원리를 설명하겠다. 아울러 실험을 통해 검증된 과전류 보호회로의 동작 결과를 살펴보겠다.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.433-436
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• 1998

Hot carrier induceed the performance degradation of sense amplifier circuit in DRAM has been measured and analyzed using 0.8.mu.m CMOS process. Simulation and experimental results show that the degradation of the MOS devices affects the decrease of the half-Vcc, voltage gain and the increase of the sensing voltage gain and the increase of the sensing voltage. The dominant degradation mechanism is the capacitance imblance in the bit-line pair. We carried out the spice simulation to investigate the degradation of the sense amplifier circuit.

• Proceedings of the Optical Society of Korea Conference
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• 2003.02a
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• pp.330-331
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• 2003

분포형 광섬유 센서시스템은 일정한 길이의 연속적인 광섬유 및 광케이블을 매질로 하여 길이 방향에서 생기는 투과율 또는 산란 특성의 변화를 통해 물리량의 변화와 그 위치를 감지하는 시스템을 말한다. 그 중에서 광섬유 내부의 브릴루앙 산란효과를 이용하여 광케이블 주위에 진동, 압력등에 매우 민감한 분포형 광섬유센서를 구성하고 외부로부터의 침입 유무와 위치를 파악함과 동시에 주요시설물의 감시 및 진단이 가능하도록 한다. (중략)

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.3
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• pp.1-7
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• 2014

This paper describes the implementation of high speed comparator for the ATE (automatic test equipment) system. The comparator block is composed of continuous comparator, differential difference amplifier(DDA) and output stage. For the wide input dynamic range of 0V to 5V, and for the high speed operation (1~800MHz), high speed rail-to-rail amplifier is used in the first stage. And hysteresis circuits, pre-amp and latch are followed for high speed operation. To measure the difference of output signals between the two devices under test (DUTs), a DDA is applied because it can detect the differences of both common signals and differential signals. This comparator chip was implemented with $0.18{\mu}m$ BCDMOS process and can compare the signal difference of 5mV up to the frequency range of 800 MHz. The chip area of the comparator is $620{\mu}m{\times}830{\mu}m$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.521-524
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• 2009

Response to nerve stimulation platform for implementing measures to detect finger movement has been functioning as an important factor. This stimulated finger on the nerve and muscle responses would vary. In other words, the finger movement of the muscle response to nerve stimulation and sensing Actuator for the H/W development is needed. In addition, a low power embedded CPU based on the top was used. H/W configuration portion of the isolation power, constant current control, High impedance INA, amplifier parts, and the stimulus mode and the Micro-control the status of current, AD converter Low Data obtained through the processing system is implemented.

• Journal of IKEEE
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• v.20 no.2
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• pp.167-170
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• 2016

Replica bit-line technique is used for making enable signal of sense amplifier which accurately tracks bit-line of SRAM. However, threshold voltage variation in the replica bit-line circuit changes the cell current, which results in variation of the sense amplifier enable time, $T_{SAE}$. The variation of $T_{SAE}$ makes the sensing operation unstable. In this paper, in addition to conventional replica bit-line delay ($RBL_{conv}$), dual replica bit-line delay (DRBD) and multi-stage dual replica bit-line delay (MDRBD) which are used for reducing $T_{SAE}$ variation are briefly introduced, and the maximum possible number of on-cell which can satisfy $6{\sigma}$ sensing yield is determined through simulation at a supply voltage of 0.6V with 14nm FinFET technology. As a result, it is observed that performance of DRBD and MDRBD is improved 24.4% and 48.3% than $RBL_{conv}$ and energy consumption is reduced which 8% and 32.4% than $RBL_{conv}$.