• Title/Summary/Keyword: 가드 링

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Silicon Substrate Coupling Modeling, Analysis, and Substrate Parameter Extraction Method for RF Circuit Design (RF 회로 설계를 위한 실리콘 기판 커플링 모델링, 해석 및 기판 파라미터 추출)

  • Jin, Woo-Jin;Eo, Yung-Seon;Shim, Jong-In
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.38 no.12
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    • pp.49-57
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    • 2001
  • In this paper, equivalent circuit model and novel model parameter extraction method of a silicon(Si) substrate are presented. Substrate coupling through Si-substrate is quantitatively investigated by analyzing equivalent circuit with operating frequency and characteristic frequencies (i.e., pole and zero frequency) of a system. For the experimental verification of the equivalent circuit and parameter extraction method, test patterns are designed and fabricated in standard CMOS technology with various isolation distances, substrate resistivity, and guard-ring structures. Then, these are measured in l00MHz-20GHz frequency range by using vector network analyzer. It is shown that the equivalent-circuit-based HSPICE simulation results using extracted parameters have excellent agreement with the experimental results. Thus, the proposed equivalent circuit and parameter extraction methodology can be usefully employed in mixed-signal circuit design and verification of a circuit performance.

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I-V Characteristics of SAGCM APD by Varing Guard-Ring Depth (SAGCM APD 에서의 가드링 형태에 따른 I-V 특성 연구)

  • 현경숙;백영미
    • Proceedings of the Optical Society of Korea Conference
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    • 2003.07a
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    • pp.100-101
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    • 2003
  • 본 논문은 초고속 광통신용 검출기로 사용되고 있는 InP/InGaAs Avalanche Photodiode (APD)에 대한 연구로서 구조 변화에 따른 APD의 특성에 대해 연구하였다. 채택된 APB의 기본 구조는 Separated Absorption, Grading, Charge and Multiplication (SAGCM)구조로 u-InP 의 두께 3.5$\mu\textrm{m}$에~2.9$\mu\textrm{m}$ 만큼 Zn diffusion 하였으며, u-InGaAs 의 흡수층 두께는 0.8$\mu\textrm{m}$ 로 하였다. charge sheet 층의 도핑 농도는 ~ 3.5 $\times$ 10/sup 12//cm/sup 2/ 이고, 전극 구조는 back side illumination type이다. (중략)

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Effect on Metal Guard Ring in Breakdown Characteristics of SiC Schottky Barrier Diode (금속 가드 링이 SiC 쇼트키 다이오드의 항복전압에 미치는 영향)

  • Kim, Seong-Jin
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.18 no.10
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    • pp.877-882
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    • 2005
  • In order to fabricate a high breakdown SiC-SBD (Schottky barrier diode), we investigate an effect on metal guard ring (MGR) in breakdown characteristics of the SiC-SBD. The breakdown characteristics of MGR-type SiC-SBD is significantly dependent on both the guard ring metal and the alloying time of guard ring metal. The breakdown characteristics of MGR-type SiC-SBDs are essentially improved as the alloying time of guard ring metal is increased. The SiC-SBD without MGR shows less than 200 V breakdown voltage, while the SiC-SBD with Al MGR shows approximately 700 V breakdown voltage. The improvement in breakdown characteristics is attributed to the field edge termination effect by the MGR, which is similar to an implanted guard ring-type SiC-SBD. There are two breakdown origins in the MGR-type SiC-SBD. One is due to a crystal defects, such as micropipes and stacking faults, in the Epi-layers and the SiC substrate, and occurs at a lower electric field. The other is due to the destruction of guard ring metal, which occurs at a higher electric field. The demolition of guard ring metal is due to the electric field concentration at an edge of Schottky contact metal.

Fabrication of InP/InGaAs Avlanche Photodeode with Floating Guard Ring by Double Diffusion (Floating Guard Ring 구조를 갖는 InP/InGaAs Avalanche Photodiode의 이중확산 방법에 의한 제작)

  • 박찬용;강승구;현경숙;김정수;김홍만
    • Korean Journal of Optics and Photonics
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    • v.7 no.1
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    • pp.66-71
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    • 1996
  • We analyzed and fabricated InP/InGaAs avalanche photodiode (APD) having floating guard ring (FGR). Since the FGR-APD is very simple to fabricate and highly reliable, the fabrication of FGR-APD and its application to the optical receiver are very useful and interesting. A double zinc diffusion was employed to fabricate and one dimensional electric field analysis was used for design. Two dimensional gain measurement showed that the FGR suppressed gain at the curved edge, indicating the successful behavior as a guard ring. The fabricated device had 35 GHz of gain-bandwidth product, and showed the sensitivity of -31.9 dBm at a bit error rate of $10^{-9}$ when it was applied to a 2.5 Gbps optical receiver.

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전자공급에 따른 원형 이온빔 플라즈마 특성연구

  • Park, Ju-Yeong;Im, Yu-Bong;Kim, Ho-Rak;Kim, Jong-Guk;Lee, Seung-Hun;Choe, Won-Ho
    • Proceedings of the Korean Vacuum Society Conference
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    • 2014.02a
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    • pp.226.1-226.1
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    • 2014
  • 이온빔 소스는 반도체 및 디스플레이 공정에 있어, 표면 에칭 및 증착 등 여러 응용 분야에 활발히 이용되고 있다. 본 연구에 사용된 원형 이온빔 소스는 선형 이온빔 소스의 가장자리에서의 특성 분석을 위해 제작되었으며, 높은 직류전압과 자기장 공간에서 플라즈마를 방전시키고 발생된 이온들을 가속시켜 높은 에너지의 이온빔을 발생시킨다. 이온빔 특성 분석을 위해 전위지연 탐침과 패러데이 탐침을 개발하였다. 전위지연 탐침은 격자판에 전압을 인가하여 선택적으로 이온을 수집하고, 이온의 에너지분포함수를 측정한다. 패러데이 탐침은 이온 수집기와 가드링으로 구성되어 수집기 표면에 일정한 플라즈마 쉬스를 형성하여 정확한 이온전류밀도를 측정한다. 본 연구에서는, 아르곤 기체를 이용하여 기체유량(8~12 sccm) 및 방전전압(1~2 kV)에 따라 방전전류 16~54 mA, 소모전력 16~108 mW의 특성을 보였다. 운전압력은 0.4~0.54 mTorr이며, 이온소스로부터 18 cm 거리에서 이온전류밀도와 이온에너지분포를 측정하였다. 또한, 중공음극선을 이용하여 인위적으로 전자를 이온 소스에서 발생된 플라즈마에 공급하고 이온빔 및 플라즈마의 특성 변화를 위 시스템에서 분석하였다.

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A Study on the Characteristics Comparison of Single Chip and Two Chip Transceiver for the Fiber Optic Modules (광모듈용 단일 칩 및 2 칩 트랜시버의 특성비교 연구)

  • Chai Sang-Hoon;Jung Hyun-Chae
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.5 s.347
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    • pp.48-53
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    • 2006
  • This paper describes the electrical characteristics of monolithic optical transceiver circuitry being used in the fiber optic modules. It has been designed and fabricated, and compared with two chips version transceiver when operates at 155.52 Mbps data rates. To avoid noise and interference between transmitter and receiver on one chip, layout techniques such as special placement, power supply separation, guard ring, and protection wall were used in the design. To compare the two kind of fiber optic modules using each chip, single chip version has similar properties to two chip version in the electrical characteristics as noise and others.

Implications for Japan's National REDD+ Strategies - Focused on Joint Credit Mechanism (JCM) - (일본 REDD+의 국가 전략 및 시사점 - 양국간 크레딧 메커니즘(JCM)을 중심으로 -)

  • Park, Jeongmook;Seo, Hwanseok;Lee, Jungsoo
    • Journal of Korean Society of Forest Science
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    • v.105 no.2
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    • pp.238-246
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    • 2016
  • The study aims to examine Japan's National REDD+ Strategies prepared for Post-2020 and the status of its implementation by organizations in Japan, and then to suggest the potential REDD+ countermeasures against Joint Credit Mechanism (JCM) for Republic of Korea and their implications. As for the technical limitations of the guidelines of REDD+ under the JCM, it is pointed out that forests located at the place with less potential safeguard intervention tend to be selected as the target area for a project and that, as reference emission trend changes depending on the basic year of the baseline, differences could occur among the amounts of greenhouse gas emission. In addition, it is pointed out that the result of the calculation of the displacement of emissions, or leakeage, in REDD+, can have an uncertainty, since the calculation is done by just multiplying leakage area by certain coefficients, without considering the size of the leakage area. Furthermore, the lack of implementation guideline or methodologies for a project level is also pointed out as a limitation, considering that there are only some national and sub-national monitoring guidelines at present. Finally, internationally accepted guidelines for safeguard and its sub-items needed to be prepared, as current safeguard policy only includes lists without detailed items. Such things mentioned above are all related to, and can lead to the problem of double counting of items in Nested Approach etc., as well as of the distribution of credits. Therefore, Republic of Korea should take these into consideration when implementing its REDD+ projects.

Design of a Single Chip CMOS Transceiver for the Fiber Optic Modules (광통신 모듈용 단일칩 CMOS 트랜시버의 설계)

  • 채상훈;김태련;권광호
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.2
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    • pp.1-8
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    • 2004
  • This paper describes the design of monolithic optical transceiver circuitry being used as a part of the fiber optic modules. It has been designed in 0.6 ${\mu}{\textrm}{m}$ 2-poly 3 metal silicon CMOS analog technology and operates at 155.52 Mbps(STM-1) data rates. It drives laser diode to transmit intensity modulated optical signal according to 155.52 Mbps electrical data from system. Also, it receives 155.52 Mbps optical data that transmitted from other systems and converts it to electrical data using photo diode and amplifier. To avoid noise and interference between transmitter and receiver on one chip, layout techniques such as special placement, power supply separation, guard ring, and protection wall were used in the design. The die area is 4 ${\times}$ 4 $\textrm{mm}^2$ and the estimated power dissipation is less than 900 ㎽ with a single 5 V supply.

Implementation of a Single Chip CMOS Transceiver for the Fiber Optic Modules (광통신 모듈용 단일 칩 CMOS트랜시버의 구현)

  • 채상훈;김태련
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.9
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    • pp.11-17
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    • 2004
  • This paper describes the implementation of monolithic optical transceiver circuitry being used as a part of the fiber optic modules. It has been fabricated in 0.6 ${\mu}{\textrm}{m}$ 2-poly 3-metal silicon CMOS analog technology and operates at 155.52 Mbps(STM-1) data rates. It drives laser diode to transmit intensity modulated optical signal according to 155.52 Mbps electrical data from system. Also, it receives 155.52 Mbps optical data that transmitted from other systems and converts it to electrical data using photo diode and amplifier. To avoid noise and interference between transmitter and receiver on one chip, layout techniques such as special placement, power supply separation, guard ring, and protection wall were used in the design. The die area is 4 ${\times}$ 4 $\textrm{mm}^2$, and it has 32.3 ps rms and 335.9 ps peak to peak jitter on loopback testing. the measured power dissipation of whole chip is 1.15 W(230 mW) with a single 5 V supply.

A Predictive Connection Admission Control Using Neural Networks for Multiclass Cognitive Users Radio Networks (멀티 클래스 인지 사용자 네트워크에서 신경망을 이용한 예측 연결수락제어)

  • Lee, Jin-Yi
    • Journal of Advanced Navigation Technology
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    • v.17 no.4
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    • pp.435-441
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    • 2013
  • This paper proposes a neural net based-predictive connection admission control (CAC) scheme for multiclass users in wireless cognitive radio networks. We classifies cognitive users(cu) into real and non real time services, and then permit only real time services to reserve the demanded resource for spectrum handoff in guard channel for provisioning the desired QoS. Neural net is employed to predict primary user's arrival on time and demanded channels. Resource scheduling scheme is based on $C_IA$(cognitive user I complete access) shown in this paper. For keeping primary users from interference, the CAC is performed on only cognitive user not primary user. Simulation results show that our schemes can guarantee the desired QoS by cognitive real time services.