• Journal of Sensor Science and Technology
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• v.20 no.4
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• pp.260-265
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• 2011

The silicon vertical hall devices are fabricated using a modified bipolar process. It consists of the thin p-layer at Si-$SiO_2$, interface and n-epi layer without $n^+$buried layer to improve the sensitivity and influence of interface effects. Experimental samples are a sensor type I with and type H without p+isolation dam adjacent to the center current electrode. The experimental results for both type show a more high current-related sensitivity than the former's vertical hall devices. The sensitivity of type H and type I are about 150 V/AT and 340 V/AT, respectively. This sensor's behavior can be explained by the similar J-FET model.

• Korean Journal of Optics and Photonics
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• v.12 no.4
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• pp.312-319
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• 2001

We proposed a B-RWG LD (Buried-ridge waveguide laser diode) having more merits than a conventional RWG-LD. It's ridge width is controlled easily, it has the advantage of being more planar than the RWG-LD and it is possible to control refractive index with growth layer thickness. Before fabricating the device, we designed the optimal device for single mode, high efficiency and high power operation. From theoretical analysis, we have to control the $d_2, d_3$ layer thicknesses for lateral effective index difference, $\Delta_{nL}$ to be higher than critical value, and simultaneously consider the ridge width for single mode and low threshold current operation. As a result, it is possible to make a single mode LD having the ridge width of $6~9{\mu}m$ if the lateral effective index difference was controlled properly. perly.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.274-283
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• 2014

In this paper, the epi layer of npn SOI HBT with n+ buried layer has been studied through Sentaurus process and device simulator. The doping value of the deposited epi layer has been varied for the npn HBT to achieve improved $f_tBV_{CEO}$ product (397 GHzV). As the $BV_{CEO}$ value is higher for low value of epi layer doping, higher supply voltage can be used to increase the $f_t$ value of the HBT. At 1.8 V $V_{CE}$, the $f_tBV_{CEO}$ product of HBT is 465.5 GHzV. Further, the film thickness of the epi layer of the SOI HBT has been scaled for better performance (426.8 GHzV $f_tBV_{CEO}$ product at 1.2 V $V_{CE}$). The addition of this HBT module to fully depleted SOI CMOS technology would provide better solution for realizing wireless circuits and systems for 60 GHz short range communication and 77 GHz automotive radar applications. This SOI HBT together with SOI CMOS has potential for future high performance SOI BiCMOS technology.

• Proceedings of the KIEE Conference
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• 1997.07d
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• pp.1270-1273
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• 1997

We have investigated the latchup characteristics of BL/BILLI retrograde twin well CMOS that has the high energy ion implanted buried layer to intend for more improvement of latchup compare to conventional retrograde well and BILLI structures. We explored the dependence of various latchup characteristics such as n+ trigger latchup and p+ trigger latchup on the buried layer implant doses. We show various DC latchup characteristics that allow us to evaluate each technology and suggest guidelines for the reduction of latchup susceptibility.

• Korean Journal of Metals and Materials
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• v.46 no.1
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• pp.39-43
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• 2008

PSII (Plasma Source Ion Implantation) using high density pulsed ICP source was employed to implant oxygen ions in Si wafer. The PSII technique can achieve a nominal oxygen dose of $3 {\times}10^{17}atoms/cm^2$ in implantation time of about 20min. In order to prevent oxidation of SOI layer during high temperature annealing, the wafer was capped with $2,000{\AA}$ $Si_3N_4 $ by PECVD. Cross-sectional TEM showed that continuous $500{\AA}$ thick buried oxide layer was formed with $300{\AA}$ thick top silicon layer in the sample. This study showed the possibility of SOI fabrication using the plasma source ion implantation with pulsed ICP source.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.415-419
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• 1999

Many bipolar logic circuit of conventional occurred problem of speed delay according to deep saturation state of vertical NPN Transistor. In order to remove minority carries of the base region at changing signal in conventional bipolar logic circuit, we made transistor which is composed of NPN transistor shortened buried layer under the Base region, PNP transistor which is merged in base, epi layer and substrate. Also the Ring-Oscillator for measuring transmission time-delay per gate was designed as well. The structure of Gate consists of the vertical NPN Transistor, substrate and Merged PNP Transistor. In the result, we fount that tarriers which are coming into intrinsic Base from Emitter and the portion of edge are relatively a lot, so those make Base currents a lot and Gain is low with a few of collector currents because of cutting the buried layer of collector of conventional junction area. Merged PNP Transistor's currents are low because Base width is wide and the difference of Emitter's density and Base's density is small. we get amplitude of logic voltage of 200mv, the minimum of transmission delay-time of 211nS, and the minimum of transmission delay-time per gate of 7.26nS in AC characteristic output of Ring-Oscillator connected Gate.

• Advances in nano research
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• v.3 no.1
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• pp.49-54
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• 2015

The structure represents symmetrical metal electrode (gate 1) - front $SiO_2$ layer - n-Si nanowire FET - buried $SiO_2$ layer - metal electrode (gate 2). At the symmetrical gate voltages high conductive regions near the gate 1 - front $SiO_2$ and gate 2 - buried $SiO_2$ interfaces correspondingly, and low conductive region in the central region of the NW are formed. Possibilities of applications of nanosize FETs at the deep inversion and depletion as a distributed capacitance are demonstrated. Capacity density is an order to ${\sim}{\mu}F/cm^2$. The charge density, it distribution and capacity value in the nanowire can be controlled by a small changes in the gate voltages. at the non-symmetrical gate voltages high conductive regions will move to corresponding interfaces and low conductive region will modulate non-symmetrically. In this case source-drain current of the FET will redistributed and change current way. This gives opportunity to investigate surface and bulk transport processes in the nanosize inversion channel.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.251-254
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• 2001

This paper describes an efficiency improvement of buried contact solar cell (BSCS) with a structure of MgF$_2$/CeO$_2$/Ag/Cu/Ni grid/n$^{+}$ emitter/p-type Si base/p$^{+}$/Al. Theoretical and experimental investigations were performed on a double layer antireflection (DLAR) coating of MgF$_2$/CeO$_2$. We investigated CeO$_2$ films as an AR layer because they have a proper refractive index of 2.46 and demonstrate the same lattice constant as Si substrate. An optimized DLAR coating shewed a reflectance as low as 2.04 % in the wavelengths ranged from 0.4 ${\mu}{\textrm}{m}$ to 1.1 ${\mu}{\textrm}{m}$. BCSC cell efficiency was improved from 16.2 % without any AR coating to 19.9 % by employing DLAR coatings. Further details on MgF$_2$/CeO$_2$ DLAR coatings on the BCSC cells are presented in this paper.per.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1065-1068
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• 2003

For the first time, high quality ultra-thin strained Si/SiGe on Insulator (SGOI) substrate with total SGOI thickness( $T_{Si}$ + $T_{SiGe}$) of 13 nm is developed to combine the device benefits of strained silicon and SOI. In the case of 6- 10 nm-thick top silicon, 100-110 % $I_{d,sat}$ and electron mobility increase are shown in long channel nFET devices. However, 20-30% reduction of $I_{d,sat}$ and electron mobility are observed with 3 nm top silicon for the same long channel device. These results clearly show that the FETs operates with higher performance due to the strain enhancement from the insertion of SiGe layer between the top silicon layer and the buried oxide(BOX) layer. The performance degradation of the extremely thin( 3 nm ) top Si device can be attributed to the scattering of the majority carriers at the interfaces.

• Korean Journal of Optics and Photonics
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• v.10 no.6
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• pp.518-523
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• 1999

In thi, study, we made experiments to fonn a mesa shape by meltback method with various concentration of solutions and found that unsaturated (20%) InGaAsP (1.55 !-tm) solution at a growth temperature was the most suitable for the formation of a mesa ,hape on the wafer which has an InGaAsP active layer and an InP cap layer on an n-InP substrate. It was difficult to form a proper mesa shape for the fabrication of PBH-LDs only by the meltback method; therefore, we fabricated PBH-LDs by forming the mesa shape with the meltback method after wet etching and by growing a current-blocking layer successively. As the electrical and optical charaleri,tiecs of MQW-PBH-LDs fabricated by above methods, when the cavity length was $300{\mu}m$, the threshold current was about 10 mA, internal quantum efficiency 82%, internal loss $9.2cm^{-1}$, and characteristic temperature was 65 K at $25~45^{\circ}C$ and 42 K at $45~65^{\circ}C$. /TEX>.