• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.319-319
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• 2013

Even though the fabrication methods of metal oxide based thin film capacitor have been well established such as RF sputtering, Sol-gel, metal organic chemical vapor deposition (MOCVD), ion beam assisted deposition (IBAD) and pulsed laser deposition (PLD), an applicable capacitor of printed circuit board (PCB) has not realized yet by these methods. Barium Strontium Titanate (BST) and other high-k ceramic oxides are important materials used in integrated passive devices, multi-chip modules (MCM), high-density interconnect, and chip-scale packaging. Thin film multi-layer technology is strongly demanded for having high capacitance (120 nF/$mm^2$). In this study, we suggest novel multi-layer thin film capacitor design and fabrication technology utilized by plasma assisted deposition and photolithography processes. Ba0.6Sr0.4TiO3 (BST) was used for the dielectric material since it has high dielectric constant and low dielectric loss. 5-layered BST and Pt thin films with multi-layer sandwich structures were formed on Pt/Ti/$SiO_2$/Si substrate by RF-magnetron sputtering and DC-sputtering. Pt electrodes and BST layers were patterned to reveal internal electrodes by photolithography. SiO2 passivation layer was deposited by plasma-enhanced chemical vapor deposition (PE-CVD). The passivation layer plays an important role to prevent short connection between the electrodes. It was patterned to create holes for the connection between internal electrodes and external electrodes by reactive-ion etching (RIE). External contact pads were formed by Pt electrodes. The microstructure and dielectric characteristics of the capacitors were investigated by scanning electron microscopy (SEM) and impedance analyzer, respectively. In conclusion, the 0402 sized thin film multi-layer capacitors have been demonstrated, which have capacitance of 10 nF. They are expected to be used for decoupling purpose and have been fabricated with high yield.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.11a
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• pp.171-174
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• 1994

The drive towards ultra-large-scale integrated circuits a continuous intermetal dielectric films for multi layer interconection. Optimum condition of remote plasma enhanced chemical vapour deposition(RPECVD) was achieved by orthogonal array method. Chracteristics of SiO$_2$ films deposited by using remote PECVD with N$_2$O gas were investigated. Etching rate of SiO$_2$ films in P-echant was about 6[A/s] that was the same as the thermal oxide. The films a showed high breakdown voltage of 7(MV/cm) and a resistivity of Bx10$\^$13/[$\Omega$cm] at 7(MV/cm). The interface Trap density of SiO$_2$ has been shown excel lent properties of 5x10$\^$10/[/$\textrm{cm}^2$eV]. It was observed that the dielectric constant dropped to a value of 4. 29 for 150 [W] RF power.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.632-634
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• 2002

Transparent dielectric layer having color-filter function in front panel for PDP(Plasma Display Panel) was successfully fabricated and characterized. Transparent dielectric layer in front panel was made of glass based on $PbO-SiO_2-B_2O_3$ ternary system. The change of properties with content variation of oxide colorants in transparent dielectric layer having color-filter function was systematically accessed. It was demonstrated that the optimized content of oxide colorants to parent glass could greatly increase up contrast ratio and color temperature without significantly degrading luminance.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.45-49
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• 2001

We have investigated physical and electrical properties of the Hf $O_2$/HfS $i_{x}$/ $O_{y}$ thin film for alternative gate dielectrics in the metal-oxide-semiconductor device. The oxidation of Hf deposited directly on the Si substrate results in the H $f_{x}$/ $O_{y}$ interfacial layer and the high-k Hf $O_2$film simultaneously. Interestingly, the post-oxidation N2 annealing of the H102/H1Si70y thin films reduces(increases) the thickness of an amorphous HfS $i_{x}$/ $O_{y}$ layer(Hf $O_2$ layer). This phenomenon causes the increase of the effective dielectric constant, while maintaining the excellent interfacial properties. The hysteresis window in C-V curves and the midgap interface state density( $D_{itm}$) of Hf $O_2$/HfS $i_{x}$/ $O_{y}$ thin films less than 10 mV and ~3$\times$10$^{11}$ c $m^{-2}$ -eV without post-metallization annealing, respectively. The leakage current was also low (1$\times$10-s A/c $m^2$ at $V_{g}$ = +2 V). It is believed that these excellent results were obtained due to existence of the amorphous HfS $i_{x}$/ $O_{y}$ buffer layer. We also investigated the charge trapping characteristics using Fowler-Nordheim electron injection: We found that the degradation of Hf $O_2$/HfS $i_{x}$/ $O_{y}$ gate oxides is more severe when electrons were injected from the gate electrode.e electrode.e.e electrode.e.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.6
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• pp.580-585
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• 2004

Silicon dioxide (SiO$_2$) is widely used as a gate dielectric material for thin film transistors (TFT) and semiconductor devices. In this paper, SiO$_2$ films were grown by APCVD(Atmospheric Pressure chemical vapor deposition) at the high temperature. Experimental investigations were carried out as a function of $O_2$ gas flow ratios from 0 to 200 1pm. This article presents the SiO$_2$ gate dielectric studies in terms of deposition rate, refrative index, FT-IR, C-V for the gate dielectric layer of thin film transistor applications. We also study defect passivation technique for improvement interface or surface properties in thin films. Our passivation technique is Forming Gas Annealing treatment. FGA acts passivation of interface and surface impurity or defects in SiO$_2$ film. We used RTP system for FGA and gained results that reduced surface fixed charge and trap density of midgap value.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.12
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• pp.809-813
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• 2016

We investigated a SiC-based hydrogen gas sensor with MIS (metal-insulator-semiconductor) structure for high temperature applications. The sensor was fabricated by $Pd/TiO_2/SiC$ structure, and a thin titanium dioxide ($TiO_2$) layer was exploited for sensitivity improvement. In the experiment, dependences of I-V characteristics and capacitance response properties on hydrogen gas concentrations from 0 to 2,000 ppm were analyzed at room temperature to $400^{\circ}C$. As the result, our sensor using $TiO_2$ dielectric layer showed possibilities with regard to use in hydrogen gas sensors for high-temperature applications.

• ETRI Journal
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• v.27 no.1
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• pp.118-121
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• 2005

Silicon dioxide ($SiO_2$) films prepared by plasma-enhanced atomic-layer deposition were successfully grown at temperatures of $100\;to\;250^{\circ}C$, showing self-limiting characteristics. The growth rate decreases with an increasing deposition temperature. The relative dielectric constants of $SiO_2$ films are ranged from 4.5 to 7.7 with the decrease of growth temperature. A $SiO_2$ film grown at $250^{\circ}C$ exhibits a much lower leakage current than that grown at $100^{\circ}C$ due to its high film density and the fact that it contains deeper electron traps.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• KIEE International Transactions on Electrophysics and Applications
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• v.3C no.2
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• pp.66-69
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• 2003

Various semiconductor nanowires such as GaN, GaP, InP, Si$_3$N$_4$, SiO$_2$/Si, and SiC were coated conformally with aluminum oxide (Al$_2$O$_3$) layers by atomic layer deposition (ALD) using trimethylaluminum (TMA) and distilled water ($H_2O$) at a temperature of 20$0^{\circ}C$. Transmission electron microscopy (TEM) revealed that A1203 cylindrical shells conformally coat the semiconductor nanowires. This study suggests that the ALD of $Al_2$O$_3$ on nanowires is a promising method for preparing cylindrical dielectric shells for coaxially gated nanowire field-effect transistors.

• Electrical & Electronic Materials
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• v.9 no.4
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• pp.336-343
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• 1996

We have studied the preparation and the properties of $Ba_{1-x}$Sr$_{x}$TiO$_{3}$(BST) thin films by using the sol-gel method. Through the comparison of the effects of various solvents and additives in making solutions, we establish the production method of the stable solution which generates the high quality of BST film. We also set up the heat-treatment conditions for depositing the BST thin film through the TGA and XRD analyses. Through the comparison of the surface conditions of BST films deposited on Pt/Ta/SiO$_{2}$/Si and Pt/Ti/SiO$_{2}$/Si substrates, we find that Ta is more efficient diffusion barrier of Si than Ti so that Ta layer prevents the formation of hillocks. We fabricate the planar type capacitor and measure the dielectric properties of the BST thin film deposited on the Pt/Ta/SiO$_{2}$/Si substrate. Dielectric constant and dielectric loss tangent at 1V, 10kHz, and leakage current density at 3V of the BST thin film are 339, 0.052 and 13.3.mu.A/cm$^{2}$, respectively.ely.