• Title/Summary/Keyword: $GF(2^m)$ Multiplication

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Implementation of a LSB-First Digit-Serial Multiplier for Finite Fields GF(2m) (유한 필드 GF(2m)상에서의 LSB 우선 디지트 시리얼 곱셈기 구현)

  • Kim, Chang-Hun;Hong, Chun-Pyo;U, Jong-Jeong
    • The KIPS Transactions:PartA
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    • v.9A no.3
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    • pp.281-286
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    • 2002
  • In this paper we, implement LSB-first digit-serial systolic multiplier for computing modular multiplication $A({\times})B$mod G ({\times})in finite fields GF $(2^m)$. If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of regularity, modularity, and unidirectional data flow, it shows good extension characteristics with respect to m and L.

High Performance Elliptic Curve Cryptographic Processor for $GF(2^m)$ ($GF(2^m)$의 고속 타원곡선 암호 프로세서)

  • Kim, Chang-Hoon;Kim, Tae-Ho;Hong, Chun-Pyo
    • Journal of KIISE:Computer Systems and Theory
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    • v.34 no.3
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    • pp.113-123
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    • 2007
  • This paper presents a high-performance elliptic curve cryptographic processor over $GF(2^m)$. The proposed design adopts Lopez-Dahab Montgomery algorithm for elliptic curve point multiplication and uses Gaussian normal basis for $GF(2^m)$ field arithmetic operations. We select m=163 which is the smallest value among five recommended $GF(2^m)$ field sizes by NIST and it is Gaussian normal basis of type 4. The proposed elliptic curve cryptographic processor consists of host interface, data memory, instruction memory, and control. We implement the proposed design using Xilinx XCV2000E FPGA device. Based on the FPGA implementation results, we can see that our design is 2.6 times faster and requires significantly less hardware resources compared with the previously proposed best hardware implementation.

A Base AOP Bit-Parallel Non-Systolic for $AB^2+C$ Computing Unit for $GF(2^m)$ ($GF(2^m)$상의 AOP 기반 비-시스토릭 병렬 $AB^2+C$연산기)

  • Hwang Woon-Taek
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.9
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    • pp.1538-1544
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    • 2006
  • This paper proposes a non-systolic parallel $AB^2+C$ Computing unit based on irreducible AOP order m of $GF(2^m)$. Proposed circuit have only AND gates and EX-OR gates, composes of cyclic shift operation, multiplication operation power operation power-sum operation and addition operation using a merry irreducible AOP. Suggested operating a method have an advantage high speed data processing, low power and integration because of only needs AND gates and EX-OR gates. $AB^2+C$ computing unit has delay-time of $T_A+(1+[log^m_2])T_X$.

A New Parallel Multiplier for Type II Optimal Normal Basis (타입 II 최적 정규기저를 갖는 유한체의 새로운 병렬곱셈 연산기)

  • Kim Chang-Han;Jang Sang-Woon;Lim Jong-In;Ji Sung-Yeon
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.16 no.4
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    • pp.83-89
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    • 2006
  • In H/W implementation for the finite field, the use of normal basis has several advantages, especially, the optimal normal basis is the most efficient to H/W implementation in GF($2^m$). In this paper, we propose a new, simpler, parallel multiplier over GF($2^m$) having a type II optimal normal basis, which performs multiplication over GF($2^m$) in the extension field GF($2^{2m}$). The time and area complexity of the proposed multiplier is same as the best of known type II optimal normal basis parallel multiplier.

Elliptic Curve Scalar Point Multiplication Using Radix-4 Modified Booth's Algorithm (Radix-4 Modified Booth's 알고리즘을 응용한 타원곡선 스칼라 곱셈)

  • 문상국
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.8 no.6
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    • pp.1212-1217
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    • 2004
  • The main back-bone operation in elliptic curve cryptosystems is scalar point multiplication. The most frequently used method implementing the scalar point multiplication, which is performed in the upper level of GF multiplication and GF division, has been the double-and-add algorithm, which is recently challenged by NAF(Non-Adjacent Format) algorithm. In this paper, we propose a more efficient and novel scalar multiplication method than existing double-and-add by applying redundant receding which originates from radix-4 Booth's algorithm. After deriving the novel quad-and-add algorithm, we created a new operation, named point quadruple, and verified with real application calculation to utilize it. Derived numerical expressions were verified using both C programs and HDL (Hardware Description Language) in real applications. Proposed method of elliptic curve scalar point multiplication can be utilized in many elliptic curve security applications for handling efficient and fast calculations.

Implementation of Multiple-Valued Adder and Multiplier Using Current-Mode CMOS (전류모드 CMOS에 의한 다치 가산기 및 승산기의 구현)

  • Seong, Hyeon-Kyeong
    • The KIPS Transactions:PartA
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    • v.11A no.2
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    • pp.115-122
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    • 2004
  • In this paper, the multiple-valued adders and multipliers are implemented by current-mode CMOS. First, we implement the 3-valued T-gate and the 4-valued T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second we implement the circuits to be realized 2-variable 3-valued addition table and multiplication table over finite fields $GF(3^2)$, and 2-variable 4-valued addition table and multiplication table over finite fields $GF(4^2)$ with the multiple-valued T-gates. Finally, these operation circuits are simulated under $1.5\mutextrm{m}$ CMOS standard technology, $15\mutextrm{A}$ unit current, and 3.3V VDD voltage Spice. The simulation results have shown the satisfying current characteristics. The 3-valued adder and multiplier, and the 4-valued adder and multiplier implemented by current-mode CMOS is simple and regular for wire routing and possesses the property of modularity with cell array. Also, since it is expansible for the addition and multiplication of two polynomials in the finite field with very large m, it is suitable for VLSI implementation.

Design of a systolic radix-4 finite-field multiplier for the elliptic curve cryptosystem (타원곡선 암호를 위한 시스톨릭 Radix-4 유한체 곱셈기의 설계)

  • Kim, Ju-Young;Park, Tae-Geun
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.695-698
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    • 2005
  • The finite-field multiplication can be applied to the wide range of applications, such as signal processing on communication, cryptography, etc. However, an efficient algorithm and the hardware design are required since the finite-field multiplication takes much time to compute. In this paper, we propose a radix-4 systolic multiplier on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed standard-basis multiplier is mathematically developed to map on low-cost systolic cell, so that the proposed systolic architecture is suitable for VLSI design. Compared to the bit-serial and digit-serial multipliers, the proposed multiplier shows relatively better performance with low cost. We design and synthesis $GF(2^{193})$ finite-field multiplier using Hynix $0.35{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.

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An Architecture of the Fast Parallel Multiplier over Finite Fields using AOP (AOP를 이용한 유한체 위에서의 고속 병렬연산기의 구조)

  • Kim, Yong-Tae
    • The Journal of the Korea institute of electronic communication sciences
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    • v.7 no.1
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    • pp.69-79
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    • 2012
  • In this paper, we restrict the case as m odd, n=mk, and propose and explicitly exhibit the architecture of a new parallel multiplier over the field GF($2^m$) with a type k Gaussian period which is a subfield of the field GF($2^n$) implements multiplication using the parallel multiplier over the extension field GF($2^n$). The complexity of the time and area of our multiplier is the same as that of Reyhani-Masoleh and Hasan's multiplier which is the most efficient among the known multipliers in the case of type IV.

A Study on Implementation of Multiple-Valued Arithmetic Processor using Current Mode CMOS (전류모드 CMOS에 의한 다치 연산기 구현에 관한 연구)

  • Seong, Hyeon-Kyeong;Yoon, Kwang-Sub
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.8
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    • pp.35-45
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    • 1999
  • In this paper, the addition and the multiplicative algorithm of two polynomials over finite field $GF(p^m)$ are presented. The 4-valued arithmetic processor of the serial input-parallel output modular structure on $GF(4^3)$ to be performed the presented algorithm is implemented by current mode CMOS. This 4-valued arithmetic processor using current mode CMOS is implemented one addition/multiplication selection circuit and three operation circuits; mod(4) multiplicative operation circuit, MOD operation circuit made by two mod(4) addition operation circuits, and primitive irreducible polynomial operation circuit to be performing same operation as mod(4) multiplicative operation circuit. These operation circuits are simulated under $2{\mu}m$ CMOS standard technology, $15{\mu}A$ unit current, and 3.3V VDD voltage using PSpice. The simulation results have shown the satisfying current characteristics. The presented 4-valued arithmetic processor using current mode CMOS is simple and regular for wire routing and possesses the property of modularity. Also, it is expansible for the addition and the multiplication of two polynomials on finite field increasing the degree m and suitable for VLSI implementation.

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Design of a systolic radix-4 finite-field multiplier for the elliptic curve cryptography (타원곡선 암호를 위한 시스톨릭 Radix-4 유한체 곱셈기 설계)

  • Park Tae-Geun;Kim Ju-Young
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.3 s.345
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    • pp.40-47
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    • 2006
  • The finite-field multiplication can be applied to the elliptic curve cryptosystems. However, an efficient algorithm and the hardware design are required since the finite-field multiplication takes much time to compute. In this paper, we propose a radix-4 systolic multiplier on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed standard-basis multiplier is mathematically developed to map on low-cost systolic cells, so that the proposed systolic architecture is suitable for VLSI design. Compared to the bit-parallel, bit-serial and systolic multipliers, the proposed multiplier has relatively effective high performance and low cost. We design and synthesis $GF(2^{193})$ finite-field multiplier using Hynix $0.35{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.