• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.10
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• pp.447-450
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• 2003

This paper presents a process optimization of antireflection (AR) coating on crystalline Si solar cells. Theoretical and experimental investigations were performed on a double-layer AR (DLAR) coating of MgF$_2$/CeO$_2$. We investigated CeO$_2$ films as an AR layer because they have a proper refractive index of 2.46 and demonstrate the same lattice constant as Si substrate. RF sputter grown CeO$_2$ film showed strong dependence on a deposition temperature. The CeO$_2$ deposited at 40$0^{\circ}C$ exhibited a strong (111) preferred orientation and the lowest surface roughness of 6.87 $\AA$. Refractive index of MgF$_2$ film was measured as 1.386 for the most of growth temperature. An optimized DLAR coating showed a reflectance as low as 2.04% in the wavelengths ranged from 0.4${\mu}{\textrm}{m}$ to 1.1${\mu}{\textrm}{m}$. We achieved the efficiencies of solar cells greater than 15% with 3.12% improvement with DLAR coatings. Further details on MgF$_2$, CeO$_2$ films, and cell fabrication parameters are presented in this paper.

• 한국초전도학회:학술대회논문집
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• v.15
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• pp.51-51
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• 2005

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.186-189
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• 2002

The MFIS capacitors were fabricated using a metalorganic decomposition method. Thin layers of $CeO_2$ were deposited as a buffer layer on Si substrate and BLT thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated. X-ray diffraction was used to determine the phase of the BLT thin films and the quality of the $CeO_2$ layer. The morphology of films and the interface structures of the BLT and the $CeO_2$ layers were investigated by scanning electron microscopy. The width of the memory window in the C-V curves for the MFIS structure is 4.78 V. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory FETs with large memory window.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.6
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• pp.546-549
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• 2007

As a rule, high temperature superconducting coated conductors have multi-layered buffers consisting of seed, diffusion barrier and cap layers. Multi-buffer layer deposition requires longer fabrication time. This is one of main reasons which increases fabrication cost. Thus, single buffer layer deposition seems to be important for practical coated conductor process. In this study, a single layered buffer deposition of $CeO_2$ for low cost coated conductors has been tried using thermal evaporation technique. 100 nm-thick $CeO_2$ layers deposited by thermal evaporation were found to act as a diffusion layer. $1\;{\mu}m-thick$ SmBCO superconducting layers were deposited by thermal co-evaporation on the $CeO_2$ buffered Ni-5%W substrate. Critical current of 90 A/cm was obtained for the SmBCO coated conductors.

• 한국초전도학회:학술대회논문집
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• v.10
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• pp.56-60
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• 2000

Cube texture를 갖는 Ni기판위에 MOCVD(Metal Chemical Vapor Deposition)를 이용하여 NiO, CeO$_2$, YBCO 박막을 제조하였다. NiO(200)와 CeO$_2$(200) buffer layer는 450${\sim}$470$^{\circ}$C에서 10분간 MOCVD방법으로 (100)<001>Ni 기판위에 직접 증착하였다. 제조된 NiO, CeO$_2$ buffer layer는 조직이 치밀하며 표면의 상태가 매우 좋으며 Ni기판 위에 epitaxial하게 성장하였다. NiO는 Ni기판과 NiO<100>//Ni<100>의 방위관계를 가지고 성장하였으며, CeO$_2$는 증착조건에 따라 CeO$_2$ <100>//Ni<100> 및 CeO$_2$ <110>//Ni<100> 의 방위관계를 가지고 성장하였다. 증착된 NiO막과 CeO$_2$막에서 균열은 발생하지 않았다. MOCVD법으로 표면에 biaxial texture를 갖는 ceramic buffer를 증착시킨 NiO/Ni및 CeO$_2$/Ni 기판위에 YBCO박막을 MOCVD법으로 제조하였다. YBCO막은 기판온도 800$^{\circ}$C,증착압력 10torr, 산소분압을 0.7torr로 하여 10분간 행하였다. 공급원료의 조성에 따라 YBCO의 막의 texture와 형성되는 상이 변화되었다. NiO/Ni및 CeO$_2$/Ni 기판 위에 증착된 YBCO막은 c축 배향성을 가지고 성장하였으며, -scan 및 ${\varphi}$ -scan으로 측정한 (500)면의 in-plane과 (110)면의 out-of-plane의 FWHM(Full Width Half Maximum)값은 각각 10$^{\circ}$ 미만으로 우수하였다.

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 2002.10b
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• pp.439-440
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• 2002

Nano-Crystalline $CeO_2$ particles were dispersed in deionized water with controlled slurry chemicals for CMP test. According to the CMP test, the removal rate of $SiO_2$ layer was mainly controlled by the size and crystallinity of $CeO_2$ particles which can be controlled by the heat-treatment condition during $CeO_2$ synthesis. In contrast, the removal rate of $Si_3N_4$ layer was significantly influenced by the passivation reagent which protects the $Si_3N_4$ surface layer from excessive dissolution during CMP.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.180-181
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• 2006

As a rule, high temperature superconducting coated conductors have multi-layered buffers consisting of seed, diffusion barrier and cap layers. Multi-buffer layer deposition requires longer fabrication time. This is one of main reasons which increases fabrication cost Thus, single buffer layer deposition seems to be important for practical coated conductor process. In this study, a single layered buffer deposition of $CeO_2$ for low cost coated conductors has been tried using thermal evaporation technique 100nm-thick $CeO_2$ layers deposited by thermal evaporation were found to act as a diffusion layer. $0.4{\mu}m$-thick SmBCO superconducting layers were deposited by thermal co-evaporation on the $CeO_2$ buffered Ni-W substrate. Critical current of 118A/$cm^2$ was obtained for the SmBCO coated conductors.

• 한국초전도학회:학술대회논문집
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• v.12
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• pp.38-38
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• 2002

• Journal of the Korean Vacuum Society
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• v.7 no.3
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• pp.195-200
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• 1998

We have investigated the crystal structure and electrical properties of Pt/SBT/$CeO_2$/Si(MFIS) and Pt/SBT/Si(MFS) structures for the gate oxide of ferroelectric memory. XRD spectra and SEM showed that the SBT film of SBT/$CeO_2$/Si structure had larger grain than that of SBT/Si structure. Furthermore HRTEM showed that SBT/$CeO_2$/Si had 5 nm thick $SiO_2$layer and very smooth interface but SBT/Si had 6nm thick $SiO_2$layer and 7nm thick amorphous intermediate interface. Therefore, $CeO_2$film between SBT film and Si substrate is confirmed as a good candidate for a diffusion barrier. The remanent polarization decreased and coercive voltage increased in Pt/SBT/$CeO_2/Pt/SiO_2$/Si structure. This effect may increase memory window of MFIS structure directly related to the coercive voltage. From the capacitance-voltage characteristics, the memory of Pt/SBT(140 nm)/$CeO_2$(25 nm)/Si structure were in the range of 1~2 V at the applied voltage of 4~6 V. The memory window increased with the thickness of SBT film. These results may be due to voltage applied at SBT films. The leakage currents of Pt/SBT/$CeO_2$/Si and Pt/SBT/Si were $ 10^8A/\textrm{cm}^2$ and $ 10^6 A/\textrm{cm}^2$, respectively.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2000.11a
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• pp.29-32
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• 2000

Cerium oxide thin film has been proposed as a buffer layer between the ferroelectric film and the Si substrate in Metal-Ferroelectric-Insulator-Silicon (MFIS ) structures for ferroelectric random access memory (FRAM) applications. In this study, CeO$_2$thin films were etched with Cl$_2$/Ar gas combination in an inductively coupled plasma (ICP). The highest etch rate of CeO$_2$film is 230 $\AA$/min at Cl$_2$/(Cl$_2$+Ar) gas mixing ratio of 0.2. This result confirms that CeO$_2$thin film is dominantly etched by Ar ions bombardment and is assisted by chemical reaction of Cl radicals. The selectivity of CeO$_2$to YMnO$_3$was 1.83. As a XPS analysis, the surface of etched CeO$_2$thin films was existed in Ce-Cl bond by chemical reaction between Ce and Cl. The results of XPS analysis were confirmed by SIMS analysis. The existence of Ce-Cl bonding was proven at 176.15 (a.m.u.).