• The Korean Journal of Physiology and Pharmacology
• /
• 제4권6호
• /
• pp.445-453
• /
• 2000

The present investigation tested the hypothesis that the activation of protein kinase G (PKG) leads to a phosphorylation of $Ca^{2+}-activated$ potassium channel $(K_{Ca}\;channel)$ and is involved in the activation of $K_{Ca}$ channel activity in cerebral arterial smooth muscle cells of the rabbit. Single-channel currents were recorded in cell-attached and inside-out patch configurations of patch-clamp techniques. Both molsidomine derivative 3-morpholinosydnonimine-N-ethylcarbamide $(SIN-1,\;50\;{\mu}M)$ and 8-(4-Chlorophenylthio)-guanosine-3',5'-cyclic monophosphate $(8-pCPT-cGMP,\;100\;{\mu}M),$ a membrane-permeable analogue of cGMP, increased the $K_{Ca}$ channel activity in the cell-attached patch configuration, and the effect was removed upon washout of the drugs. In inside-out patches, single-channel current amplitude was not changed by SIN-1 and 8-pCPT-cGMP. Application of ATP $(100\;{\mu}M),$ cGMP $(100\;{\mu}M),$ ATP+cGMP $(100\;{\mu}M\;each),$ PKG $(5\;U/{\mu}l),$ ATP $(100\;{\mu}M)+PKG\;(5\;U/{\mu}l),$ or cGMP $(100\;{\mu}M)+PKG\;(5\;U/{\mu}l)$ did not increase the channel activity. ATP $(100\;{\mu}M)+cGMP\;(100\;{\mu}M)+PKG\;(5\;U/{\mu}l)$ added directly to the intracellular phase of inside-out patches increased the channel activity with no changes in the conductance. The heat-inactivated PKG had no effect on the channel activity, and the effect of PKG was inhibited by 8-(4-Chlorophenylthio)-guanosine-3',5'-cyclic monophosphate, Rp-isomer $(Rp-pCPT-cGMP,\;100\;{\mu}M),$ a potent inhibitor of PKG or protein phosphatase 2A (PP2A, 1 U/ml). In the presence of okadaic acid (OA, 5 nM), PP2A had no effect on the channel activity. The $K_{Ca}$ channel activity spontaneously decayed to the control level upon washout of ATP, cGMP and PKG, and this was prevented by OA (5 nM) in the medium. These results suggest that the PKG-mediated phosphorylations of $K_{Ca}$ channels, or some associated proteins in the membrane patch increase the activity of the $K_{Ca}$ channel, and the activation may be associated with the vasodilating action.

• 전기전자학회논문지
• /
• 제17권1호
• /
• pp.71-76
• /
• 2013

본 연구에서는 AlGaN/GaN HEMT (High electron mobility transistor)를 제작하고 채널폭의 감소에 따른 특성의 변화를 고찰하였다. AlGaN/GaN 이종접합구조 기반의 기판 위에 채널의 길이는 $1{\mu}m$, 채널 폭은 각각 $0.5{\sim}9{\mu}m$가 되도록 전자선 리소그라피 방법으로 트랜지스터를 제작하였다. 게이트를 형성하지 않은 상태에서 채널의 면저항을 측정한 결과 sub-${\mu}m$ 크기로 채널폭이 작아짐에 따라 채널의 면저항이 급격히 증가하였으며, 트랜지스터의 문턱전압은 $1.6{\mu}m$와 $9{\mu}m$의 채널폭에서 -2.85 V 이었으며 $0.9{\mu}m$의 채널폭에서 50 mV의 변화, $0.5{\mu}m$에서는 350 mV로 더욱 큰 변화를 보였다. 트랜스컨덕턴스는 250 mS/mm 내외의 값으로부터 sub-${\mu}m$ 채널에서 150 mS/mm로 채널폭에 따라 감소하였다. 또한, 게이트의 역방향 누설전류는 채널폭에 따라 감소하였으나 sub-${\mu}m$ 크기에서는 감소가 둔화되었는데 채널폭이 작아짐에 따라 나타는 이와 같은 일련의 현상들은 AlGaN 층의 strain 감소로 인한 압전분극 감소가 원인이 되는 것으로 사료된다.

• Journal of Electrical Engineering and information Science
• /
• 제3권2호
• /
• pp.261-266
• /
• 1998

This paper describes the fabrication and characterization of dual-polysilicon gated surface channel 0.1$\mu\textrm{m}$ CMOSFETs using BF2 and arsenic as channel dopants. We have used and LDD structure and 40${\AA}$ gate oxide as an insulator. To suppress short channel effects down to 0.1$\mu\textrm{m}$ channel length, shallow source/drain extensions implemented by low energy implantation and SSR(Super Steep Retrograde) channel structure were used. The threshold voltages of fabricated CMOSFETs are 0.6V. The maximum transconductance of nMOSFET is 315${\mu}$S/$\mu\textrm{m}$, and that of pMOSFET is 156 ${\mu}$S/$\mu\textrm{m}$. The drain saturation current of 418 ${\mu}$A/$\mu\textrm{m}$, 187${\mu}$A/$\mu\textrm{m}$ are obtained. Subthreshold swing is 85mV/dec and 88mV/dec, respectively. DIBL(Drain Induced Barrier Lowering) is below 100mV. In the device with 2000${\AA}$ thick gate polysilicon, depletion in polysilicon near the gate oxide results in an increase of equivalent gate oxide thickness and degradation of device characteristics. The gate delay time is measured to be 336psec at operation voltage of 2V.

• 전자공학회논문지A
• /
• 제32A권8호
• /
• pp.126-132
• /
• 1995

The electrical stress of short channel polycrystalline silicon (poly-Si) thin film transistor (TFT) has been investigated. The device characteristics of short channel poly-Si TFT with 5$\mu$m channel length has been observed to be significantly degraded such as a large shift in threshold voltage and asymmetric phenomena after the electrical stress. The dominant degradation mechanism in long channel poly-Si TFT's with 10$\mu$m and 20$\mu$m channel length respectively is charage trappling in gate oxide while that in short channel device with 5.mu.m channel length is defect creation in active poly-Si layer. We propose that the increased defect density within depletion region near drain junction due to high electric field which could be evidenced by kink effect, constitutes the important reason for this significant degradation in short channel poly-Si TFT. The proposed model is verified by comparing the amounts of the defect creation and the charge trapping from the strechout voltage.

• Journal of Electrical Engineering and Technology
• /
• 제2권2호
• /
• pp.267-273
• /
• 2007

A depletion-mode MOSFET has been analyzed to evaluate its electrical behavior using a novel 3-D numerical simulation package. The characterizing analysis of the BC MOSFET was performed through short-channel narrow-channel and small-geometry effects that are investigated, in detail, in terms of the threshold voltage. The DIBL effect becomes significant for a short-channel device with a channel length of $<\;3({\mu}m)$. For narrow-channel devices the variation of the threshold voltage was sharp for $<4({\mu}m)$ due to the strong narrow-channel effect. In the case of small-geometry devices, the shift of the threshold voltage was less sensitive due to the combination of the DIBL and substrate bias effects, as compared with that observed from the short-channel and narrow-channel devices. The characterizing analysis of the narrow-channel and small-geometry devices, especially with channel width of $<\;4({\mu}m)$ and channel area of $<\;4{\times}4({\mu}m^2)$ respectively, can be accurately performed only from a 3-D numerical simulation due to their sharp variations in threshold voltages.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 1992년도 춘계학술대회 논문집
• /
• pp.91-96
• /
• 1992

The nonvolatile SNOSFET EEPROM memory devices with the channel width and iength of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$], 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$] and 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$] were fabricated by using the actual CMOS 1 [Mbit] process technology. The charateristics of I$\_$D/-V$\_$D/, I$\_$D/-V$\_$G/ were investigated and compared with the channel width and length. From the result of measuring the I$\_$D/-V$\_$D/ charges into the nitride layer by applying the gate voltage, these devices ere found to have a low conductance state with little drain current and a high conductance state with much drain current. It was shown that the devices of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$] represented the long channel characteristics and the devices of 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$] and 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$] represented the short channel characteristics. In the characteristics of I$\_$D/-V$\_$D/, the critical threshold voltages of the devices were V$\_$w/ = +34[V] at t$\_$w/ = 50[sec] in the low conductance state, and the memory window sizes wee 6.3[V], 7.4[V] and 3.4[V] at the channel width and length of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$], 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$], 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$], respectively. The positive logic conductive characteristics are suitable to the logic circuit designing.

• Journal of Electrical Engineering and information Science
• /
• 제2권3호
• /
• pp.99-104
• /
• 1997

A novel driving theory on the electrohydrodynamic (EHD) pump driven by traveling electric fields without the temperature gradient is proposed. The equations of the generating pressure and the flow rate are derived. The EHD micropump is fabricated by micromachining technology and tested. The channel heights are 50$\mu\textrm{m}$, 100$\mu\textrm{m}$ and 200$\mu\textrm{m}$ are respectively an the channel width is 3 mm. The spacing and width of the electrodes are both 40$\mu\textrm{m}$. The maximum pressure is 70.3 Pa, 35.4 Pa and 17.2 pa at he frequency of 0.2Hz for each channel height (50$\mu\textrm{m}$, 100$\mu\textrm{m}$ and 200$\mu\textrm{m}$) and the maximum flow rate is 0.90x10\ulcorner ${\mu}$$\ell$/min, 1.88x10\ulcorner ${\mu}$$\ell$/min and 4.85x10\ulcorner ${\mu}$$\ell$/min at the frequency of 0.4H for each channel height.

• 한국정보통신학회논문지
• /
• 제16권4호
• /
• pp.785-792
• /
• 2012

본 연구에서는 고속 및 저전력 스위칭 소자 응용을 위하여 n-채널 무접합 및 반전모드 MuGFET 와 p-채널 무접합 및 축적모드 MuGFET의 기판전압에 따른 전류-전압 특성을 측정하고 비교 분석하였다. 기판전압에 따른 문턱전압과 포화 드레인 전류 변화로부터 n-채널 소자에서는 반전모드 소자가 무접합 소자보다 변화량이 크며 p-채널 소자에서는 무접합 소자가 축적모드 소자보다 변화량이 큰 것을 알 수 있었다. 전달컨덕턴스 변화는 n-채널 소자보다 p-채널 소자의 변화량이 큰 것을 알 수 있었다. 그리고 subthreshold swing 특성으로부터 n-채널 소자와 p-채널 무접합 소자는 기판전압 변화에 따라 S값의 변화가 거의 없지만 p-채널 축적모드 소자는 기판전압이 양의 방향으로 증가할 때 S 값이 증가하는 것으로 관측되었다. 기판전압을 이용한 고속 및 저전력 스위칭 소자 응용 측면에서는 n-채널 소자에서는 반전모드 소자가 p-채널 소자에서는 무접합 소자가 더 좋은 특성을 보였다.

• 대한전자공학회논문지SD
• /
• 제37권12호
• /
• pp.1-9
• /
• 2000

미세구조 N-채널 MOSFET의 게이트-소스 전압에 의존하는 유효 채널 캐리어 이동도와 소스 및 드레인 기생저항의 정확한 분리 추출을 위해서 새로운 ERM-방법을 제안하였다. ERM-방법은 선형영역에서 동작하는 게이트 길이가 다른 두개의 소자($W_m/L_m=30{\mu}m/0.6{\mu}m, 30{\mu}m/1{mu}m$)에 적용되었고 유효 채널 캐리어 이동도를 모델링하고 추출하는 과정에서 게이트-소스 전압에 의존하는 소스 및 드레인 기생저항의 영향을 고려하였다. ERM-방법으로 추출된 특성변수들을 사용한 해석적 모델식과 소자의 측정데이터를 비교해본 결과 오차가 거의 없이 일치하는 것을 확인하였다. 따라서, ERM-방법을 사용하면 대칭구조 및 비대칭구조 소자의 유효 채널 캐리어 이동도, 소스 및 드레인 기생저항과 다른 특성변수들을 정확하고 효율적으로 추출할 수 있을 것으로 기대된다.

• E2M - 전기 전자와 첨단 소재
• /
• 제6권4호
• /
• pp.330-338
• /
• 1993

Channel의 폭과 길이가 15 x 15.mu.m, 15 x 1.5.mu.m, 1.9 x 1.7.mu.m인 비휘발성 SNOSFET EEPROM 기억소자를 CMOS 1 Mbit 설계규칙에 의하여 제작하고 체널크기에 따른 $I_{D}$- $V_{G}$특성 및 스위칭 특성을 조사하여 비교하였다. 게아트에 전압을 인가하여 질화막에 전하를 주입시키거나 소거시킨 후 특성을 측정한 결과, 드레인전류가 적게 흐르는 저전도상태와 전류가 많이 흐르는 고전도상태로 되는 것을 확인하였다. 15 x 15.mu.m의 소자는 전형적인 long channel특성을 나타냈으며 15 x 1.5.mu.m, 1.9 x 1.7.mu.m는 short channel특성을 보였다. $I_{D}$- $V_{G}$ 특성에서 소자들의 임계 문턱전압은 저전도상태에서 $V_{W}$=+34V, $t_{W}$=50sec의 전압에서 나타났으며 메모리 윈도우 폭은 15 x 15.mu.m, 15 x 1.5.mu.m, 1.9 x 1.7.mu.m의 소자에서 각각 6.4V, 7.4V, 3.5V였다. 스위칭 특성조사에서 소자들은 모두 논리스윙에 필요한 3.5V 메모리 윈도우를 얻을 수 있었으며 논리회로설계에 적절한 정논리 전도특성을 가졌다.특성을 가졌다.다.다.