Handling precise timing in high-speed transceivers has always been a primary design target to achieve better performance. Many different approaches have been tried, and one of those is utilizing the beneficial nature of injection locking. Though the phenomenon was not intended for building integrated circuits at first, its coupling effect between neighboring oscillators has been utilized deliberately. Consequently, the dynamics of the injection-locked oscillator (ILO) have been explored, starting from R. Adler. As many aspects of the ILO were revealed, further studies followed to utilize the technique in practice, suggesting alternatives to the conventional frequency syntheses, which tend to be complicated and expensive. In this review, the historical analysis techniques from R. Adler are studied for better comprehension with proper notation of the variables, resulting in numerical results. In addition, how the timing jitter or phase noise in the ILO is attenuated from noise sources is presented in contrast to the clock generators based on the phase-locked loop (PLL). Although the ILO is very promising with higher cost effectiveness and better noise immunity than other schemes, unless correctly controlled or tuned, the promises above might not be realized. In order to present the favorable conditions, several strategies have been explored in diverse applications like frequency multiplication, data recovery, frequency division, clock distribution, etc. This paper reviews those research results for clock multiplication and data recovery in detail with their advantages and disadvantages they are referring to. Through this review, the readers will hopefully grasp the overall insight of the ILO, as well as its practical issues, in order to incorporate it on silicon successfully.

Radio frequency (RF) energy harvesting technology have become a reliable and promising alternative to extend the lifetime of power-constrained wireless networks by eliminating the need for batteries. This emerging technology enables the low-power wireless devices to be self-sustaining and eco-friendly by scavenging RF energy from ambient environment or dedicated energy sources. These attributes make RF energy harvesting technology feasible and attractive to an extended range of applications. However, despite being the most reliable energy harvesting technology, there are several challenges (especially power conversion efficiency, output DC voltage and sensitivity) poised for the implementation of RF energy harvesting systems. In this article, a detailed literature on RF energy harvesting technology has been surveyed to provide guidance for RF energy harvesters design. Since signal strength of the received RF power is limited and weak, high efficiency state-of-the-art RF energy harvesters are required to design for providing sufficient DC supply voltage to wireless networks. Therefore, various designs and their trade-offs with comprehensive analysis for RF energy harvesters have been discussed. This paper can serve as a good reference for the researchers to catch new research topics in the field of RF energy harvesting.

We present an approximate DRAM architecture for energy-efficient deep learning. Our key premise is that by bounding memory errors to non-critical information, we can significantly reduce DRAM refresh energy without compromising recognition accuracy of deep neural networks. To validate the key premise, we make extensive Monte-Carlo simulations for several well-known convolutional neural networks such as LeNet, ConvNet and AlexNet with the input of MINIST, CIFAR-10, and ImageNet, respectively. We assume that the highest-order 8-bits (in single precision) and 4-bits (in half precision) are protected from retention errors under the proposed architecture and then, randomly inject bit-errors to unprotected bits with various bit-error-rates. Here, recognition accuracies of the above convolutional neural networks are successfully maintained up to the 10^-5-order bit-error-rate. We simulate DRAM energy during inference of the above convolutional neural networks, where the proposed architecture shows the possibility of considerable energy saving up to 10 ~ 37.5% of total DRAM energy.

With the recent emergence of foldable electronic devices, interest in flexible organic memory is significantly growing. There are three types of flexible organic memory that have been researched so far: floating-gate (FG) memory, ferroelectric field-effect-transistor (FeFET) memory, and resistive memory. Herein, performance parameters and operation mechanisms of each type of memory device are introduced, along with a brief summarization of recent research progress in flexible organic memory.

This article highlights new opportunities of inorganic semiconductor materials for bio-implantable electronics, as a subset of 'transient' technology defined by an ability to physically dissolve, chemically degrade, or disintegrate in a controlled manner. Concepts of foundational materials for this area of technology with historical background start with the dissolution chemistry and reaction kinetics associated with hydrolysis of nanoscale silicon surface as a function of temperature and pH level. The following section covers biocompatibility of silicon, including related other semiconductor materials. Recent transient demonstrations of components and device levels for bioresorbable implantation enable the future direction of the transient electronics, as temporary implanters and other medical devices that provide important diagnosis and precisely personalized therapies. A final section outlines recent bioresorbable applications for sensing various biophysical parameters, monitoring electrophysiological activities, and delivering therapeutic signals in a programmed manner.

Complementary metal-oxide-semiconductor (CMOS) technology is now facing a power scaling limit to increase integration density. Since 1970s, multi-valued logic (MVL) has been considered as promising alternative to resolve power scaling challenge for increasing information density up to peta-scale level by reducing the system complexity. Over the past several decades, however, a power-scalable and mass-producible MVL technology has been absent so that MVL circuit and system implementation have been delayed. Recently, compact MVL device researches incorporating multiple-switching characteristics in a single device such as 2D heterojunction-based negative-differential resistance (NDR)/transconductance (NDT) devices and quantum-dot/superlattices-based constant intermediate current have been actively performed. Meanwhile, wafer-scale, energy-efficient and variation-tolerant ternary-CMOS (T-CMOS) technology has been demonstrated through commercial foundry. In this review paper, an overview for MVL development history including recent studies will be presented. Then, the status and its future research direction of MVL technology will be discussed focusing on the T-CMOS technology for peta-scale information processing in semiconductor chip.