• IEMEK Journal of Embedded Systems and Applications
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• v.6 no.3
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• pp.190-200
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• 2011

Android platform provides a content provider and a cursor mechanism to access the internal SQLite engine. Content providers not only store and retrieve data but also make it accessible to applications. Applications can only share data through content provider, since there's no common storage area that Android packages can access. Cursor is an interface that provides random read-write access to the result set returned by a database query. However, this cursor possesses two major limitations. First, a cursor does not support a join clause among cursors, since the cursor can only access a single table in the content provider. Second, the cursor is not capable of creating user-customized field in the predefined content providers. In this paper, we propose the unified cursor architecture that merges several cursors into a single virtual cursor. Cursor translation look-aside buffer (TLB), column windowing mechanism and virtual data management are the three major techniques we have adopted to implement our structure. And we also propose a delayed synchronization method between an application and a proposed unified cursor. An application can create a user-customized field and sort multiple tables using a unified cursor on Android platform.

• Journal of the Institute of Convergence Signal Processing
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• v.14 no.3
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• pp.191-204
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• 2013

In this paper, we investigated the correlation outputs of Daejeon correlator at the viewpoints of the buffer memory setting related to the fine delay tracking and the under/overflow issue in FFT modules, in order to eliminate DC-like component and phase concentration to 0 degree. As the ring buffer memory is being used for the fine delay tracking, the DC-like component in correlation outputs is generated by improper setting of data read/write address, and then that address setting method is modified to exclude a polluted FFT segment in correlation processing when crossing the port/stream boundary. The phase concentration to 0 degree at beginning of bandpass is caused by inadequate scaling factors, which may be the origins of under/overflow occurred at internal computation of FFT stage. With the revised method of the ring buffer memory setting and the scaling factors in FFT, we could obtain higher signal-to-noise ratio and flux density, compared to the previous method, through the correlation processing of true observational data.

• Journal of Korea Multimedia Society
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• v.8 no.4
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• pp.439-449
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• 2005

Distributed main memory database management systems (DMM-DBMSs) store the database in main memories of the participating sites. They provide high performance through fast access to the local databases and high speed communication among the sites. Recently, a lot of research results on DMM- DBMSs has been reported. However, to the best of our knowledge, there is no known research result on the performance of the catalog management schemes for DMM-DBMSs. In this work, we evaluated the performance of the partitioned catalog management schemes through experimental analysis. First, we classified the partitioned catalog management schemes into three categories : Partitioned Catalogs Without Caching (PCWC), Partitioned Catalogs With Incremental Caching (PCWIC), and Partitioned Catalogs With Full Caching (PCWFC). Experiments were conducted by varying the number of sites, the number of terminals per site, buffer size, write query ratio, and local query ratio. Experiments show that PCWFC outperforms the other two schemes in all cases. It also means that the performance of PCWIC gradually increases as time goes by. It should be noted that PCWFC does not guarantee high performance for disk-based distributed DBMSs in cases when the workload of individual site is high, catalog write ratio is high, or remote data objects are accessed very frequently. Main reason that PCWFC outperforms for DMM-DBMSs is that query compilation and remote catalog access can be done in a very high speed, even when the catalogs of the remote data objects are frequently updated.

• Journal of KIISE:Databases
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• v.34 no.2
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• pp.109-118
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• 2007

Recently, flash memory is used to store data in mobile computing devices such as PDAs, SmartCards, mobile phones and MP3 players. These devices need index structures like the B-tree to efficiently support some operations like insertion, deletion and search. The BFTL(B-tree Flash Translation Layer) technique was first introduced which is for implementing the B-tree on flash memory. Flash memory has characteristics that a write operation is more costly than a read operation and an overwrite operation is impossible. Therefore, the BFTL method focuses on minimizing the number of write operations resulting from building the B-tree. However, we indicate in this paper that there are many rooms of improving the performance of the I/O cost in building the B-tree using this method and it is not practical since it increases highly the usage of the SRAM memory storage. In this paper, we propose a BOF(the B-tree On Flash memory) approach for implementing the B-tree on flash memory efficiently. The core of this approach is to store index units belonging to the same B-tree node to the same sector on flash memory in case of the replacement of the buffer used to build the B-tree. In this paper, we show that our BOF technique outperforms the BFTL or other techniques.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.8A
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• pp.820-829
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• 2006

IP-based design methodology has been popularly employed for SoC design to reduce design complexity and to cope with time-to-market pressure. Due to the request for high performance of current mobile systems, embedded SoC design needs a multi-processor to manage problems of high complexity and the data processing such as multimedia, DMB and image processing in real time. Interface module for communication between system buses and processors are required, since many IPs employ different protocols. High performance processors require interface module to minimize the latency of data transmission during read-write operation and to enhance the performance of a top level system. This paper proposes an automatic interface generation system based on FSM generated from the common protocol description sequence of a bus and an IP. The proposed interface does not use a buffer which stores data temporally causing the data transmission latency. Experimental results show that the area of the interface circuits generated by the proposed system is reduced by 48.5% on the average, when comparing to buffer-based interface circuits. Data transmission latency is reduced by 59.1% for single data transfer and by 13.3% for burst mode data transfer. By using the proposed system, it becomes possible to generate a high performance interface circuit automatically.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.12
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• pp.963-967
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• 2009

The Log-structured File System (LFS) collects all modified data into a memory buffer and writes them sequentially to a segment on disk. Therefore, it has the potential to utilize the maximum bandwidth of storage devices where sequential writes are much faster than random writes. However, as disk space is finite, LFS has to conduct cleaning to produce free segments. This cleaning operation is the main reason LFS performance deteriorates when file system utilization is high. To overcome painful cleaning and reduced performance of LFS, we propose the segment space recycling (SSR) scheme that directly writes modified data to invalid areas of the segments and describe the classification method of data and segment to consider locality of reference for optimizing SSR scheme. We implement U-LFS, which employs our segment space recycling scheme in LFS, and experimental results show that SSR scheme increases performance of WOLF by up to 1.9 times in HDD and 1.6 times in SSD when file system utilization is high.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.7
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• pp.425-432
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• 2014

This paper proposes a wear-leveling algorithm that exploits the properties of SSD memories with multi-channel and multi-way architecture. When a write request arrives, the proposed algorithm classifies the stored data in DRAM buffer into hot or cold according to logical address access frequency, and performs data allocation to reduce deviation of block erase counts. It lowers the chance of increasing erase count by allocating cold data to blocks which have high erase count. Effectiveness of the proposed algorithm is verified by executing various applications on a multi-channel, multi-way SSD simulator. Experimental results show that differences in erase count among blocks is reduced by an average of 9.3%, and total erase count decreases by 4.6%, when compared to previous wear-leveling algorithm.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.1 s.343
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• pp.121-126
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• 2006

This paper report on the design and implementation of a 9.6kbps DSSS CDMA modem for a medium speed wireless link. The proposed modem provides a general purpose I/O interface with a microprocessor. The I/O interface consists of 8-bit data bus, chip enable, read/write, and interrupt pins. In transmit block, the 8-bit data delivered from the I/O interface buffer is converted to 9.6kbps serial data, which are spreaded into 76.8kcps with 8-bit PN code generated inside the modem by direct sequence method. An 8-bit training sequence is preceded in the data frame for data synchronization in receiver. In receiver block the PN code is synchronized from the received data spreaded to 76.8kcps and find the data timing from the 8-bit training sequence. We have used the Early-and-Late integration method. The modem has been implemented and verified using a Xilix FPGA board and has been fabricated as an ASIC CHIP through Hynir $0.25{\mu}m$ CMOS. The multiple accessing method is DSSS CDMA.

• Proceedings of the Korean Information Science Society Conference
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• 2006.10a
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• pp.261-266
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• 2006

최근 낸드 플래시 메모리는 임베디드 저장 장치로서 많이 사용되고 있을 뿐만 아니라 플래시 메모리의 저장 용량의 대용량화로 하드 디스크를 대체하는 SSD(solid state disk) 같은 제품이 출시되고 있다. 플래시 메모리는 하드디스크에 비하여 저전력, 빠른 접근성, 물리적 안정성 등의 장점이 있지만 읽기와 쓰기의 연산의 불균형적인 비용과 덮어 쓰기가 안 되고 쓰기 전에 해당 블록을 지워야하는 부가적인 작업을 수행해야 한다. 이와 같은 특징은 플래시 메모리의 쓰기 성능을 저하 시키고 기존의 하드디스크를 대체하는 것을 어렵게 만든다. 이와 같은 플래시 메모리의 단점을 해결하기 위해서 본 논문에서 비휘발성 메모리와 플래시 메모리를 함께 사용하는 방법을 제안한다. 최근 MRAM, FeRAM, PRAM과 같은 차세대 메모리 기술의 발전과 배터리 백업 메모리의 가격 하락으로 인하여 비휘발성 메모리의 상품적 가치가 높아지고 있다. 하지만 아직까지 용량 대비 가격이 비효율적이기 때문에 소용량의 비휘발성 메모리를 활용하여 플래시 메모리의 쓰기 연산에 대한 단점을 보완하는 방법을 제안한다. 본 논문에서는 FTL 에서 비휘발성 메모리를 쓰기 버퍼로 이용한 여러 가지 버퍼 관리 정책을 실험하였고 각 관리 정책에 따른 플래시 메모리의 성능 향상을 측정하였다. 실험을 통하여 최대로 읽기의 횟수는 90% 감소, 쓰기 횟수는 33% 감소, 소거 횟수는 50% 감소 효과를 보였다.

• Journal of Korea Multimedia Society
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• v.10 no.5
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• pp.604-611
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• 2007

Java Card has gained genera1 acceptance with standard for smart card and (U)SIM technology, and it is in distinction from native card by its post-issuance of an application and independence from hardware platforms. However, a main weak point of Java Card is its low execution speed caused by the hardware limitation and Java programming language itself. In this paper, we propose a new Java Card Installer to improve the download speed during the post-issuance of an application by resolving symbolic references to physical references in HAM. Our Resolution_In_RAM is based on the improved new RAM writing is 100,000 times faster than EEPROM writing and PageBuffer that is operated as block mode, rather than cell mode is used to write to EEPROM. Consequently, the total number of EEPROM writing are reduced 37%, and the times of downloading are reduced over 30% by using the Resolution_In_RAM-based Java Card Installer.