DOI QR코드

DOI QR Code

An Efficient Wear-Leveling Algorithm for NAND Flash SSD with Multi-Channel and Multi-Way Architecture

멀티채널과 멀티웨이 구조의 NAND 플래시 SSD를 위한 효율적인 웨어레벨링 알고리듬

  • Kim, Dong-Ho (Sogang University Department of Electric Engineering) ;
  • Hwang, Sun-Young (Sogang University Department of Electric Engineering)
  • Received : 2014.05.26
  • Accepted : 2014.06.13
  • Published : 2014.07.31

Abstract

This paper proposes a wear-leveling algorithm that exploits the properties of SSD memories with multi-channel and multi-way architecture. When a write request arrives, the proposed algorithm classifies the stored data in DRAM buffer into hot or cold according to logical address access frequency, and performs data allocation to reduce deviation of block erase counts. It lowers the chance of increasing erase count by allocating cold data to blocks which have high erase count. Effectiveness of the proposed algorithm is verified by executing various applications on a multi-channel, multi-way SSD simulator. Experimental results show that differences in erase count among blocks is reduced by an average of 9.3%, and total erase count decreases by 4.6%, when compared to previous wear-leveling algorithm.

본 논문은 멀티채널과 멀티웨이 구조를 가진 SSD의 구조적 특성을 감안한 웨어레벨링 알고리듬을 제안한다. 제안된 알고리듬은 쓰기 요청이 도착했을 때 DRAM에 저장된 데이터를 논리주소 접근 빈도에 따라 핫 데이터와 콜드 데이터로 나누고, 블록 소거횟수의 편차를 줄이도록 데이터를 할당한다. 콜드 데이터를 소거횟수가 많은 블록에 할당하여 소거횟수 증가를 억제한다. 멀티채널과 멀티웨이 구조의 SSD 시뮬레이터에 다양한 어플리케이션에서 얻어진 트레이스를 적용하여 검증한 결과, 기존의 웨어레벨링 알고리듬을 사용하는 경우에 비해 블록의 소거횟수의 차이가 평균 9.3% 줄어들고 총 소거횟수가 평균 4.6% 감소하였다.

Keywords

References

  1. S. Shim, H. Kang, S. Jung, and Y. Song, "Page mapping table caching technique for large scale NAND flash memory," in Proc. Symp. Korean Inst. Commun. Inf. Sci. (KICS), pp. 463-464, Yongpyong, Korea, Feb. 2012.
  2. J. Kim, J. Kim, S. Noh, S. Min, and Y. Cho, "A space-efficient flash translation layer for compact flash systems," IEEE Trans. Consumer Electron., vol. 48, no. 2, pp. 366-375, May 2002. https://doi.org/10.1109/TCE.2002.1010143
  3. F. Douglis, R. Caceres, F. Kaashoek, K. Li, B. Marsh, and J. Tauber, "Storage alternatives for mobile computers," in Proc. Symp. Operating Syst. Design and Implementation, pp. 25-37, Monterey, CA, Nov. 1994.
  4. S. Lim and K. Park, "An efficient NAND flash file system for flash memory storage," IEEE Trans. Comput., vol. 55, no. 7, pp. 906-912, Jul. 2006. https://doi.org/10.1109/TC.2006.96
  5. S. Boyd, A. Horvath, and D. Dornfeld, "Life-cycle assessment of NAND flash memory," IEEE Trans. Semiconductor Manufacturing, vol. 24, no. 1, pp. 117-124, Feb. 2011. https://doi.org/10.1109/TSM.2010.2087395
  6. D. Park and J. Lee, "Performance of the coupling canceller with the various window size on the multi-level cell NAND flash memory channel," J. Korean Inst. Commun. Sci., vol. 37, no. 8, pp. 706-711, Aug. 2012. https://doi.org/10.7840/kics.2012.37A.8.706
  7. D. Lee and W. Sung, "Adaptive quantization scheme for multi-level cell NAND flash memory," J. Korean Inst. Commun. Sci., vol. 38, no. 6, pp. 540-549, Jun. 2013. https://doi.org/10.7840/kics.2013.38C.6.540
  8. J. Ha and J. O, "Error correction code for NAND flash memory," J. Korean Inst. Commun. Sci., vol. 28, no. 9, pp. 58-68, Aug. 2011.
  9. E. Gal and S. Toledo, "Algorithms and data structures for flash memories," ACM Computing Surveys, vol. 37, no. 2, pp. 138-163, Jun. 2005. https://doi.org/10.1145/1089733.1089735
  10. Y. Hu, N. Xiao, and X. Liu, "An elastic error correction code technique for NAND flash-based consumer electronic devices," IEEE Trans. Consumer Electron., vol. 59, no. 1, pp. 1-8, Feb. 2013. https://doi.org/10.1109/TCE.2013.6490234
  11. N. Mielke, T. Marquart, N. Wu, J. Kessenich, H. Belgal, E. Schares, F. Trivedi, E. Goodness, and L. Nevill, "Bit error rate in NAND flash memories," in Proc. Reliability Physics Symp., pp. 9-19, Phoenix, AZ, Apr. 2008.
  12. C. Park, P. Talawar, D. Won, M. Jung, J. Im, S. Kim, and Y. Choi, "A high performance controller for NAND flash-based solid state disk," in Proc. 21st IEEE Non-Volatile Semiconductor Memory Workshop, pp. 17-30, Monterey, CA, Feb. 2006.
  13. S. Park, S. Ha, K. Bang, and E. Chung, "Design and analysis of flash translation layers for multi-channel NAND flash-based storage devices," IEEE Trans. Consumer Electron., vol. 55, no. 3, pp. 1392-1400, Aug. 2009. https://doi.org/10.1109/TCE.2009.5278005
  14. J. Kang, J. Kim, C. Park, H. Park, and J. Lee, "A multi-channel architecture for highperformance NAND flash-based storage system," J. Syst. Architecture, vol. 53, no. 9, pp. 644-658, Sept. 2007. https://doi.org/10.1016/j.sysarc.2007.01.010
  15. M. Jung, E. Wilson, D. Donofrio, J. Shalf, and M. Kandemir, "NANDFlashSim: Intrinsic latency variation aware NAND flash memory system modeling and simulation at microarchitecture level," in Proc. IEEE 28th Symp. Mass Storage Systems and Technol., pp. 1-12, San Diego, CA, Apr. 2012.
  16. M. Chiang, P. Lee, and R. Chang, "Managing flash memory in personal communication devices," in Proc. Int. Symp. Conumer Electron., pp. 177-182, Singapore, Dec. 1997.
  17. L. Chang "On efficient wear leveling for large-scale flash-memory storage systems," in Proc. ACM Symp. Applied Computing, pp. 1126-1130, Seoul, Korea, Mar. 2007.