• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.110-113
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• 1998

An analysis of the relationship between a linear amplifier chain and an analog-to-digital converter(ADC) in a digital microwave widevand receiver, with respect to sensitivity and dynamic range issues, is presented. The effects of gain, third-order intermodulation products and ADC characteristics on the performance of the receiver are illustrated and design criteria for the linear amplifier chain given a specified ADC are developed. A computer program is used to calculate theretical receiver performance based on gain and third-order intermodulation product selections. Simulated results are also presented and compared with theoretical values.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.3
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• pp.569-577
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• 1999

A wideband RF receiver for satellite mobile communications system was fabricated and evaluated of performance in low noise amplifier and high gain amplifier. The low noise amplifier used to the resistive decoupling and self-bias circuits. The low noise amplifier is fabricated with both the RF circuits and the self-bias circuits. Using a INA-03184, the high gain amplifier consists of matched amplifier type. The active bias circuitry can be used to provide temperature stability without requiring the large voltage drop or relatively high-dissipated power needed with a bias stabilized resistor. The bandpass filter was used to reduce a spurious level. As a result, the characteristics of the receiver implemented here show more than 55 dB in gain, 50.83 dBc in a spurious level and less than 1.8 : 1 in input and output voltage standing wave ratio(VSWR), especially the carrier to noise ratio is a 43.15 dB/Hz at a 1 KHz from 1537.5 MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.8A
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• pp.735-744
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• 2006

In this paper, the optimum pump light powers of optical phase conjugator(OPC) are numerically investigated as a function of amplifier spacing in 1,200 km $8{\times}40$ Gbps WDM systems with 0.1, 0.4, 0.8, or 1.6 ps/nm/km dispersion coefficient. It is confirmed that the variation of optimal pump light power dependence on amplifier spacing for NRZ transmission system is smaller than that for RZ transmission system through the evaluations and analysis of eye opening penalty(EOP) characteristics. And, in both cases of NRZ and RZ transmission, the variation of optimal pump light power is more increased as amplifier spacing becomes longer. Additionally, it is confirmed that the best amplifier spacing in NRZ and RZ transmission system is 50 km.

• ETRI Journal
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• v.29 no.5
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• pp.673-675
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• 2007

We present the design and fabrication of a 60 GHz medium power amplifier monolithic microwave integrated circuit with excellent gain-flatness for a 60 GHz radio-over-fiber system. The circuit has a 4-stage structure using microstrip coupled lines instead of metal-insulator-metal capacitors for unconditional stability of the amplifier and yield enhancement. The gains of each stage of the amplifier are modified to provide broadband characteristics of input/output matching for the first and fourth stages and to achieve higher gains for the second and third stages to improve the gain-flatness of the amplifier for wideband.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.2
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• pp.221-226
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• 2012

In this paper, wideband two-stage amplification stage was designed, fabricated and evaluated. The proposed amplification stage with a novel gain control method have a high gain, low noise and high linearity performance. It is consisted of common emitter amplifier as the first stage, cascode gain control amplifier as second stage and power detector which sense the received signal strength. The proposed amplification stage shows a total gain of 29 dB~37 dB, noise fiugre of 1.5 dB at operating band and high linearity performance as the IMD (third intermodulation distortion) level is below the noise level of the measurement equipment at the control voltage 2.0 V generated from power detector under the strong electric field condition.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.45-51
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• 2011

This paper presents a wideband low-noise amplifier (LNA) covering 800MHz~5.8GHz for various wireless communication standards by utilizing in a 0.13um CMOS technology. Particularly, the LNA consists of two stages to improve the low-noise characteristics, that is, a cascode input stage and an output buffer with noise cancellation technique. Also, a feedback resistor is exploited to help achieve wideband impedance matching and wide bandwidth. Measure results demonstrate the bandwidth of 811MHz~5.8GHz, the maximum gain of 11.7dB within the bandwidth, the noise figure of 2.58~5.11dB. The chip occupies the area of $0.7{\times}0.9mm^2$, including pads. DC measurements reveal the power consumption of 12mW from a single 1.2V supply.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.100-108
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• 2014

Low noise amplifier (LNA) is an integral component of RF receiver and frequently required to operate at wide frequency bands for various wireless system applications. For wideband operation, important performance metrics such as voltage gain, return loss, noise figure and linearity have been carefully investigated and characterized for the proposed LNA. An inductive shunt feedback configuration is successfully employed in the input stage of the proposed LNA which incorporates cascaded networks with a peaking inductor in the buffer stage. Design equations for obtaining low and high impedance-matching frequencies are easily derived, leading to a relatively simple method for circuit implementation. Careful theoretical analysis explains that input impedance can be described in the form of second-order frequency response, where poles and zeros are characterized and utilized for realizing the wideband response. Linearity is significantly improved because the inductor located between the gate and the drain decreases the third-order harmonics at the output. Fabricated in $0.18{\mu}m$ CMOS process, the chip area of this wideband LNA is $0.202mm^2$, including pads. Measurement results illustrate that the input return loss shows less than -7 dB, voltage gain greater than 8 dB, and a little high noise figure around 6-8 dB over 1.5 - 13 GHz. In addition, good linearity (IIP3) of 2.5 dBm is achieved at 8 GHz and 14 mA of current is consumed from a 1.8 V supply.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.539-540
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• 2008

This paper presents an ultra-wideband (UWB) CMOS low noise amplifier (LNA) topology that operates in 3.1-10.6GHz band. The common gate structure provides wideband input matching and flattens the passband gain. The proposed UWB amplifier is implemented in 0.18 um CMOS technology for lower band operation mode. Simulation shows a minimum NF of 2.35 dB, a power gain of $18.3{\sim}20\;dB$, better than -10 dB of input and output matching, while consuming 16.4 mW.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1054-1057
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• 2002

The design and fabrication of Q-band 3-stage monolithic microwave integrated circuit(MMIC) amplifier for WLAN are presented using 0.2$\square$ AIGaAs/lnGaAs/GaAs pseudomorphic high electron mobility transistor (PHEMT). In each stage of the MMIC, a negative feedback is used for both broadband and good stability. The measurement results are achieved as an input return loss under -4dB, an output return loss under -10dB, a gain of 14dB, and a PldB of 17dBm at Q-band(36～44GHz). These results closely match with design results. The chip size is 2.8${\times}$1.3mm$^2$. This MMIC amplifier will be used as the unit cell to develop millimeter-wave transmitters for use in wideband wireless LAN systems.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.232-238
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• 2008

In this paper, a wideband power efficient 2.2 GHz - 4.9 GHz Medium Power Amplifier (MPA), has been designed and fabricated using $0.8{\mu}m$ SiGe BiCMOS process technology. Passive elements such as parallel-branch spiral inductor, metal-insulator-metal (MIM) capacitor and three types of resistors are all integrated in this process. This MPA is a two stage amplifier with all matching components and bias circuits integrated on-chip. A P1dB of 17.7 dBm has been measured with a power gain of 8.7 dB at 3.4 GHz with a total current consumption of 30 mA from a 3 V supply voltage at $25^{\circ}C$. The measured 3 dB bandwidth is 2.7 GHz and the maximum Power Added Efficiency (PAE) is 41 %, which are very good results for a fully integrated Medium PA. The fabricated circuit occupies a die area of $1.7mm{\times}0.8mm$.