• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.110-113
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• 1998

An analysis of the relationship between a linear amplifier chain and an analog-to-digital converter(ADC) in a digital microwave widevand receiver, with respect to sensitivity and dynamic range issues, is presented. The effects of gain, third-order intermodulation products and ADC characteristics on the performance of the receiver are illustrated and design criteria for the linear amplifier chain given a specified ADC are developed. A computer program is used to calculate theretical receiver performance based on gain and third-order intermodulation product selections. Simulated results are also presented and compared with theoretical values.

• 한국정보통신학회논문지
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• 제3권3호
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• pp.569-577
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• 1999

본 논문에서는 이동위성통신용 광대역 수신단을 저잡음증폭기와 고이득증폭단으로 나누어서 구현 및 성능 평가를 하였다. 저잡음증폭기의 설계ㆍ제작에는 저잡음 GaAs FET인 ATF-10136파 내부정합된 MMIC인 VNA-25를 이용하였으며, 저잡음증폭기의 입력단 정합회로는 저항 결합회로, 전원회로는 자기 바이어스 회로를 사용하였다. INA-03184를 이용한 고이득증폭단은 양단 정합된 단일 증폭기 형태로 제작하였으며, 바이어스 안정화 저항을 사용하여 회로의 전압강하 및 전력손실을 가능한 줄이고 온도 안정성을 고려하여 능동 바이어스 회로를 사용하였으며, 스퓨리어스를 감쇠시키기 위해서 저잡음증폭기와 고이득증폭단 사이에 감쇠 특성이 우수한 대역통과 필터를 사용하였다. 측정 결과, 사용 주파수 대역내에서 55dB 이상의 이득, 50.83dBc의 스퓨리어스 특성 및 1.8. 1 이하의 입ㆍ출력 정재파비를 나타내었으며, 특히 1537.5 MHz에서 1 KHz 떨어진 점에서의 C/N비가 43.15 dB/Hz를 나타냄으로써 설계시 목표로 했던 사양을 모두 만족시켰다.

• 한국통신학회논문지
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• 제31권8A호
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• pp.735-744
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• 2006

In this paper, the optimum pump light powers of optical phase conjugator(OPC) are numerically investigated as a function of amplifier spacing in 1,200 km $8{\times}40$ Gbps WDM systems with 0.1, 0.4, 0.8, or 1.6 ps/nm/km dispersion coefficient. It is confirmed that the variation of optimal pump light power dependence on amplifier spacing for NRZ transmission system is smaller than that for RZ transmission system through the evaluations and analysis of eye opening penalty(EOP) characteristics. And, in both cases of NRZ and RZ transmission, the variation of optimal pump light power is more increased as amplifier spacing becomes longer. Additionally, it is confirmed that the best amplifier spacing in NRZ and RZ transmission system is 50 km.

• ETRI Journal
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• 제29권5호
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• pp.673-675
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• 2007

We present the design and fabrication of a 60 GHz medium power amplifier monolithic microwave integrated circuit with excellent gain-flatness for a 60 GHz radio-over-fiber system. The circuit has a 4-stage structure using microstrip coupled lines instead of metal-insulator-metal capacitors for unconditional stability of the amplifier and yield enhancement. The gains of each stage of the amplifier are modified to provide broadband characteristics of input/output matching for the first and fourth stages and to achieve higher gains for the second and third stages to improve the gain-flatness of the amplifier for wideband.

• 한국전자통신학회논문지
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• 제7권2호
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• pp.221-226
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• 2012

본 논문에서는 광대역 (400 MHz~2000 MHz) 2단 증폭단을 설계, 제작 및 측정하였다. 제안한 증폭단은 새로운 구조의 이득제어 방식을 적용하여 고이득, 저잡음지수 및 높은 선형성 특성을 구현하였다. 증폭단은 공통 에미터 구조의 초단 증폭기 및 캐스코드 구조의 가변이득 증폭기. 입력신호의 크기를 감지하는 전력감지회로로 구성하였다. 제안한 증폭단은 설계 대역에서 전체이득 29 dB~37 dB, 잡음지수 1.5 dB을 나타내었고, 강전계 입력 조건에서 전력감지회로에서 발생되는 제어전압 2.0V인 조건에서 3차 상호변조 왜곡 신호의 크기는 측정 장비의 잡음레벨 보다 낮은 특성을 나타내어 높은 선형성 특성을 나타내었다.

• 대한전자공학회논문지SD
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• 제48권12호
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• pp.45-51
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• 2011

본 논문에서는 $0.13{\mu}m$ CMOS 공정을 사용하여 800MHz~5.8GHz 대역 내 다양한 무선통신 표준을 포함하는 광대역 저잡음 증폭기(wideband-LNA)를 구현하였다. 저잡음 특성을 개선하기 위하여 제작한 LNA는 두 단으로 구성되었으며, 입력캐스코드 단 및 잡음신호만을 상쇄시키는 출력 버퍼단으로 구성하였다. 또한, 피드백 저항을 이용함으로써, 광대역 임피던스 매칭 효과 및 넓은 대역폭을 구현하였다. 측정결과, 811MHz~5.8GHz의 주파수 응답과 대역폭 내에서 최대 11.7dB의 전력이득 및 2.58~5.11dB의 잡음지수(NF)를 얻었다. 제작한 칩은 $0.7{\times}0.9mm^2$의 면적을 가지며 1.2V의 전원전압에서 12mW의 낮은 전력을 소모 한다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권1호
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• pp.100-108
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• 2014

Low noise amplifier (LNA) is an integral component of RF receiver and frequently required to operate at wide frequency bands for various wireless system applications. For wideband operation, important performance metrics such as voltage gain, return loss, noise figure and linearity have been carefully investigated and characterized for the proposed LNA. An inductive shunt feedback configuration is successfully employed in the input stage of the proposed LNA which incorporates cascaded networks with a peaking inductor in the buffer stage. Design equations for obtaining low and high impedance-matching frequencies are easily derived, leading to a relatively simple method for circuit implementation. Careful theoretical analysis explains that input impedance can be described in the form of second-order frequency response, where poles and zeros are characterized and utilized for realizing the wideband response. Linearity is significantly improved because the inductor located between the gate and the drain decreases the third-order harmonics at the output. Fabricated in $0.18{\mu}m$ CMOS process, the chip area of this wideband LNA is $0.202mm^2$, including pads. Measurement results illustrate that the input return loss shows less than -7 dB, voltage gain greater than 8 dB, and a little high noise figure around 6-8 dB over 1.5 - 13 GHz. In addition, good linearity (IIP3) of 2.5 dBm is achieved at 8 GHz and 14 mA of current is consumed from a 1.8 V supply.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.539-540
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• 2008

This paper presents an ultra-wideband (UWB) CMOS low noise amplifier (LNA) topology that operates in 3.1-10.6GHz band. The common gate structure provides wideband input matching and flattens the passband gain. The proposed UWB amplifier is implemented in 0.18 um CMOS technology for lower band operation mode. Simulation shows a minimum NF of 2.35 dB, a power gain of $18.3{\sim}20\;dB$, better than -10 dB of input and output matching, while consuming 16.4 mW.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.1054-1057
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• 2002

The design and fabrication of Q-band 3-stage monolithic microwave integrated circuit(MMIC) amplifier for WLAN are presented using 0.2$\square$ AIGaAs/lnGaAs/GaAs pseudomorphic high electron mobility transistor (PHEMT). In each stage of the MMIC, a negative feedback is used for both broadband and good stability. The measurement results are achieved as an input return loss under -4dB, an output return loss under -10dB, a gain of 14dB, and a PldB of 17dBm at Q-band(36～44GHz). These results closely match with design results. The chip size is 2.8${\times}$1.3mm$^2$. This MMIC amplifier will be used as the unit cell to develop millimeter-wave transmitters for use in wideband wireless LAN systems.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권3호
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• pp.232-238
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• 2008

In this paper, a wideband power efficient 2.2 GHz - 4.9 GHz Medium Power Amplifier (MPA), has been designed and fabricated using $0.8{\mu}m$ SiGe BiCMOS process technology. Passive elements such as parallel-branch spiral inductor, metal-insulator-metal (MIM) capacitor and three types of resistors are all integrated in this process. This MPA is a two stage amplifier with all matching components and bias circuits integrated on-chip. A P1dB of 17.7 dBm has been measured with a power gain of 8.7 dB at 3.4 GHz with a total current consumption of 30 mA from a 3 V supply voltage at $25^{\circ}C$. The measured 3 dB bandwidth is 2.7 GHz and the maximum Power Added Efficiency (PAE) is 41 %, which are very good results for a fully integrated Medium PA. The fabricated circuit occupies a die area of $1.7mm{\times}0.8mm$.