• 청정기술
• /
• 제29권4호
• /
• pp.255-261
• /
• 2023

파워반도체는 전력의 변환, 변압, 분배 및 전력제어 등을 감당하는데 사용되는 반도체이다. 최근 세계적으로 고전압 파워반도체의 수요는 다양한 산업분야에 걸쳐 증가하고 있는 추세이며 해당 산업에서는 고전압 IGBT 부품의 최적화 연구가 절실한 상황이다. 고전압 IGBT개발을 위해서 wafer의 저항값 설정과 주요 단위공정의 최적화가 완성칩의 전기적특성에 큰 변수가 되며 높은 항복전압(breakdown voltage) 지지를 위한 공정 및 최적화 기술 확보가 중요하다. 식각공정은 포토리소그래피공정에서 마스크회로의 패턴을 wafer에 옮기고, 감광막의 하부에 있는 불필요한부분을 제거하는 공정이고, 이온주입공정은 반도체의 제조공정 중 열확산기술과 더불어 웨이퍼 기판내부로 불순물을 주입하여 일정한 전도성을 갖게 하는 과정이다. 본 연구에서는 IGBT의 3.3 kV 항복전압을 지지하는 ring 구조형성의 중요한 공정인 field ring 식각실험에서 건식식각과 습식식각을 조절해 4가지 조건으로 나누어 분석하고 항복전압확보를 위한 안정적인 바디junction 깊이형성을 최적화하기 위하여 TEG 설계를 기초로 field ring 이온주입공정을 4가지 조건으로 나누어 분석한 결과 식각공정에서 습식 식각 1스텝 방식이 공정 및 작업 효율성 측면에서 유리하며 링패턴 이온주입조건은 도핑농도 9.0E13과 에너지 120 keV로, p-이온주입 조건은 도핑농도 6.5E13과 에너지 80 keV로, p+ 이온주입 조건은 도핑농도 3.0E15와 에너지 160 keV로 최적화할 수 있었다.

• 한국산업보건학회지
• /
• 제29권3호
• /
• pp.310-321
• /
• 2019

Objectives: The purpose of this study was to investigate types and characteristics of chemical substances used in LCD(Liquid crystal display) panel manufacturing process. Methods: The LCD panel manufacturing process is divided into the fabrication(fab) process and module process. The use of chemical substances by process was investigated at four fab processes and two module processes at two domestic TFT-LCD(Thin film transistor-Liquid crystal display) panel manufacturing sites. Results: LCD panels are manufactured through various unit processes such as sputtering, chemical vapor deposition(CVD), etching, and photolithography, and a range of chemicals are used in each process. Metal target materials including copper, aluminum, and indium tin oxide are used in the sputtering process, and gaseous materials such as phosphine, silane, and chlorine are used in CVD and dry etching processes. Inorganic acids such as hydrofluoric acid, nitric acid and sulfuric acid are used in wet etching process, and photoresist and developer are used in photolithography process. Chemical substances for the alignment of liquid crystal, such as polyimides, liquid crystals, and sealants are used in a liquid crystal process. Adhesives and hardeners for adhesion of driver IC and printed circuit board(PCB) to the LCD panel are used in the module process. Conclusions: LCD panels are produced through dozens of unit processes using various types of chemical substances in clean room facilities. Hazardous substances such as organic solvents, reactive gases, irritants, and toxic substances are used in the manufacturing processes, but periodic workplace monitoring applies only to certain chemical substances by law. Therefore, efforts should be made to minimize worker exposure to chemical substances used in LCD panel manufacturing process.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 1999년도 제17회 학술발표회 논문개요집
• /
• pp.65-65
• /
• 1999

Dry etching technique provides more easy controllability on the etch profile such as anisotropic etching than wet etching process and the results of lots of researches on the characterization of various plasmas or ion beams for semiconductor etching have been reported. Chlorine-based plasmas or chlorine ion beam have been often used to etch several semiconductor materials, in particular Si-based materials. We have studied the effect of He flow rate on the Si and SiO2 dry etching using chlorine-based plasma. Experiments were performed using reactive ion etching system. RF power was 300W. Cl2 gas flow rate was fixed at 58.6 sccm, and the He flow rate was varied from 0 to 120 sccm. Fig. 1 presents the etch depth of si layer versus the etching time at various He flow rate. In case of low He flow rate, the etch rate was measured to be negligible for both Si and SiO2. As the He flow increases over 30% of the total inlet gas flow, the plasma state becomes stable and the etch rate starts to increase. In high Ge flow rate (over 60%), the relation between the etch depth and the time was observed to be nearly linear. Fig. 2 presents the variation of the etch rate depending on the He flow rate. The etch rate increases linearly with He flow rate. The results of this preliminary study show that Cl2/He mixture plasma is good candidate for the controllable si dry etching.

• 한국재료학회지
• /
• 제23권6호
• /
• pp.322-328
• /
• 2013

The relationship the between electrical properties and surface roughness (Ra) of a wet-etched silicon wafer were studied. Ra was measured by an alpha-step process and atomic force microscopy (AFM) while varying the measuring range $10{\times}10$, $40{\times}40$, and $1000{\times}1000{\mu}m$. The resistivity was measured by assessing the surface resistance using a four-point probe method. The relationship between the resistivity and Ra was explained in terms of the surface roughness. The minimum error value between the experimental and theoretical resistivities was 4.23% when the Ra was in a range of $10{\times}10{\mu}m$ according to AFM measurement. The maximum error value was 14.09% when the Ra was in a range of $40{\times}40{\mu}m$ according to AFM measurement. Thus, the resistivity could be estimated when the Ra was in a narrow range.

• 한국신재생에너지학회:학술대회논문집
• /
• 한국신재생에너지학회 2009년도 추계학술대회 논문집
• /
• pp.349-349
• /
• 2009

High quality ZnO:Al films were prepared on glass substrates by in-line RF magnetron sputtering and their surface morphologies were modified by wet-etching process in dilute acid solution to improve optical properties for application to silicon thin film solar cells as front electrode. The as-deposited films show a strong preferred orientation in [001] direction under our experimental conditions. A low resistivity below $5{\times}10^{-4}{\Omega}{\cdot}cm$ and high optical transmittance above 80% in a visible range are achieved in the films deposited at optimized conditions. After wet-etching, the surface morphologies of the films are changed dramatically depending on the deposition conditions, especially working pressure. The optical properties such as total/diffuse transmittance, haze and angular resolved distribution of light are varied significantly with the surface morphology feature, whereas the electrical properties are seldom changed. The cell performances of silicon thin film solar cells fabricated on the textured films are also evaluated in detail with comparison of commercial $SnO_2$:F films.

• 한국정밀공학회:학술대회논문집
• /
• 한국정밀공학회 2005년도 춘계학술대회 논문집
• /
• pp.1522-1526
• /
• 2005

In this study, the fabrication of large area silicon mirror is accomplished by anisotropic etching using MEMS for implementation of integrated optical pickup and the process condition is also established for improving the mirror surface roughness. Until now, few results have been reported about the production of highly stepped $9.74^{\circ}$ off-axis-cut silicon wafer using wet etching. In addition rough surface of the mirror is achieved in case of long etching time. Hence a novel method called magnetorheolocal finishing is introduced to enhancing the surface quality of the mirror plane. Finally, areal peak to valley surface roughness of mirror plane is reduced about 100nm in large area of $mm^2$ and it is applicable to optical pickup using infrared wavelength.

• 정보저장시스템학회논문집
• /
• 제1권2호
• /
• pp.182-187
• /
• 2005

A large area micro mirror is an optical element that functions as changing an optical path by reflection in integrated optical system. We fabricated the large area silicon mirror by anisotropic etching using MEMS for implementation of integrated optical pickup. In this work, we report the optimum conditions to better fabricate and design, greatly improve mirror surface quality. To obtain mirror surface of $45^{\circ},\;9.74^{\circ}$ off-axis silicon wafer from (100) plane was used in etching condition of $80^{\circ}C$ with 40wt.% KOH solution. After wet etching, polishing process by MR fluid was applied to mirror surface for reduction of roughness. In the next step, after polymer coating on the polished Si wafer, the Si mirror was fabricated by UV curing using a trapezoid bar-type way structure. Finally, we obtained peak to valley roughness about 50 nm in large area of $mm^2$ and it is applicable to optical pickup using blu-ray wavelength as well as infrared wavelength.

• 센서학회지
• /
• 제9권3호
• /
• pp.224-232
• /
• 2000

표면 미세가공 공정에서 Al 공정을 이용하면 Al 전극의 제작에 의해 접촉 저항이나 선 저항 등을 줄여 전기적인 신호 손실을 줄일 수 있고, 산화막을 희생층으로 사용하는 간단한 공정에 의해 Al 구조물 제작이 가능한 장점을 지닌다. 그러나 실제 공정에서는 Al 전극이나 Al 구조물이 희생층 제거 시에 사용되는 HF 용액에 의해서 부식되는 문제점이 있다. 이러한 문제점을 해결하기 위해 사용되는 희생층 식각액인 BHF/glycerine 혼합 용액에 대한 PSG와 Al의 기본적인 식각 특성은 표면 미세가공에서 발생하는 구조적인 제한 조건에 따라 상당히 달라진다. 본 논문에서는 이러한 희생층의 구조적 특성과 Al 박막의 증착 표면 거칠기의 변화로 인한 식각 특성의 변화를 고려하여 실제로 표면 미세가공에 적용 가능한 혼합 용액의 조건을 조사하였다. 희생층 식각 조건변화에 따른 BHF/glycerine 혼합용액의 최적 혼합비는 $NH_4F$:HF:glycerine=2:1:2에서 가장 좋은 식각 선택비를 보이는 것으로 나타났으며 이 실험 결과를 실제 Al 전극 제작에 적용한 결과 Al 패턴이 희생층 식각액에 대해서 우수한 내식성을 보였다. 또한 Al의 식각액에 대한 내식성을 향상시키기 위하여 CMP 공정을 도입하여 증착 표면을 개선시켰으며 이를 Al 구조물의 제작에 적용하여 식각 특성을 분석하였다. 이러한 분석을 통해 본 논문에서 제시한 식각 조건을 이용하면 Al 전극과 Al 구조물을 표준적인 표면 미세가공 공정을 통하여 간단하게 제작할 수 있다.

• 전자공학회논문지A
• /
• 제28A권11호
• /
• pp.902-909
• /
• 1991

A reproducible selective dry etch process of GaAs/AlGaAs Heterostructures for High Electron Mobility Transistor(HEMT) Device fabrication is developed. Using RIE mode with $CCl_{2}F_{2}$ as the basic process gas, the observed etch selectivity of GaAs layer with respect to GaAs/$Al_{0.3}Ga_{0.7}$As is about 610:1. Severe polymer deposition problem, parialy generated from the use of $CCl_{2}F_{2}$ gas only, has been significantly reduced by adding a small amount of He gas or by $O_{2}$ plasma ashing after etch process. In order to obtain an optimized etch process for HEMT device fabrication, we com pared the properties of the wet etched Schottky contact with those of the dry etched one, and set dry etch condition to approach the characteristics of Schottky diode on wet etched surface. By applying the optimized etch process, the fabricated HEMT devices have the maximum transconductance $g_{mext}$ of 224 mS/mm, and have relatively uniform distribution across the 2inch wafer in the value of 200$\pm$20mS/mm.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
• /
• pp.1038-1041
• /
• 2003

In the paper, we investigated silicon surface microstructures formed by reactive ion etching in hollow cathode system. Wet anisotropic chemical etching technique use to form random pyramidal structure on <100> silicon wafers usually is not effective in texturing of low-cost multicrystalline silicon wafers because of random orientation nature, but High density hollow cathode plasma system illustrates high deposition rate, better film crystal structure, improved etching characteristics. The etched silicon surface is covered by columnar microstructures with diameters form 50 to 100nm and depth of about 500nm. We used $SF_{6}$ and $O_{2}$ gases in HCP dry etch process. This paper demonstrates very high plasma density of $2{\times}10^{12}$ $cm^{-3}$ at a discharge current of 20 mA. Silicon etch rate of 1.3 ${\mu}s/min$. was achieved with $SF_{6}/O_{2}$ plasma conditions of total gas pressure=50 mTorr, gas flow rate=40 sccm, and rf power=200 W. Our experimental results can be used in various display systems such as thin film growth and etching for TFT-LCDs, emitter tip formations for FEDs, and bright plasma discharge for PDP applications. In this paper we directed our study to the silicon etching properties such as high etching rate, large area uniformity, low power with the high density plasma.