• Journal of the Korean Society for Precision Engineering
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• v.27 no.2
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• pp.13-19
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• 2010

Due to the rapid spread of mobile handheld devices, industrial demands for micro-scale holes with a diameter of even smaller than $10{\mu}m$ in sapphire/silicon wafers have been increasing. Holes in sapphire wafers are for heat dissipation from LEDs; and those in silicon wafers for interlayer communication in three-dimensional integrated circuit (IC). We have developed a sapphire wafer driller equipped with a 532nm laser in which a cooling chuck is employed to minimize local heat accumulation in wafer. Through the optimization of process parameters (pulse energy, repetition rate, number of pulses), quality holes with a diameter of $30{\mu}m$ and a depth of $100{\mu}m$ can be drilled at a rate of 30holes/sec. We also have developed a silicon wafer driller equipped with a 355nm laser. It is able to drill quality through-holes of $15{\mu}m$ in diameter and $150{\mu}m$ in depth at a rate of 100holes/sec.

• Journal of the Korean Society for Heat Treatment
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• v.30 no.5
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• pp.222-226
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• 2017

Recently sapphire wafer has expected as smart phone cover material, however, brittle nature of sapphire needed edge grinding processes to prevent early initiation of cracks. Electro-deposited multi-layered groove tools with $35{\mu}m$ diamond particles were studied for sapphire wafer grinding. Solid particle flow behaviors in agitated electrolyte was studied using PIV(Particle Image Velocimetry), and uniform particle distribution in Ni bond were obtained when agitating impeller was located lower part of electrolyte. Hardness values of $400{\pm}50Hv$ were maintained for retention of diamond particles in electro-deposited bond layer. Sapphire wafer edge grinding test was carried out and multi-layered $160{\mu}m$ thick diamond tool showed much greater grinding capabilities up to 2000 sapphire wafers than single-layered $50{\mu}m$ thick diamond electro-deposited tools of 420 wafers. The reason why 3 times thicker multi-layered tools than single-layered tools showed 5 times longer tool lives in grinding processes was attributed to self-dressed new diamond particles in multi-layered tools, and multi-layered diamond tools could be promising for sapphire grinding.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.8
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• pp.455-460
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• 2016

A textured front surface is required in high efficiency silicon solar cells to reduce reflectance and to improve light trapping. Wet etching with alkaline solution is usually applied for mono crystalline silicon solar cells. However, alkali texturing method is not appropriate for multi-crystalline silicon wafers due to grain boundary of random crystallographic orientation. Accordingly, acid texturing method is generally used for multi-crystalline silicon wafers to reduce the surface reflectance. To reduce reflectivity of multi-crystalline silicon wafers, double texturing method with combination of acid and reactive ion etching is an attractive technical solution. In this paper, we have studied to optimize RIE condition by different RF power condition (100, 150, 200, 250, 300 W).

• Journal of the Semiconductor & Display Technology
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• v.13 no.3
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• pp.21-25
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• 2014

The texturing is one of the most important processes for high efficiency crystalline silicon solar cells. The rear side flatness of silicon solar cell is very important for increasing the light reflectance and forming uniform back surface field(BSF) region in manufacturing high efficiency crystalline silicon solar cells. We investigated texturing difference between front and rear side of wafer by texturing of two adhered wafers. As a result, the flatter rear side was obtained by forming less pyramid size compared to the front side and improved reflectance of long wavelength and back surface field(BSF) region were also achieved. Therefore, the texturing of two adhered wafers can be expected to improve the efficiency of silicon solar cells due to increased short circuit current(Isc).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.2
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• pp.99-103
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• 2008

To improve efficiency of solar cells, it is important to make a light trapping structure to reduce surface reflectance for increasing absorption of sun light within the solar cells. One of the promising methods that can reduce surface reflectance is isotropic texturing with acid solution based on hydrofluoric acid(HF), nitric acid($HNO_3$), and organic additives. Anisotropic texturing with alkali solution is not suitable for multicrystalline silicon wafers because of its different grain orientation. Isotropic texturing with acid solution can uniformly etch multicrystalline silicon wafers unrelated with grain orientation, so we can get low surface reflectance. In this paper, the acid texturing solution is made up of only HF and $HNO_3$ for easy controlling the concentration and low cost compared to acid solution with organic additives. $HNO_3$ concentration and dipping time were varied to find the condition of minimum surface reflectance. Textured surfaces were observed Scanning Electron Microscope(SEM) and surface reflectance were measured. The best result of arithmetic mean(wavelength from 400 nm to 1000 nm) reflectance with acid texturing is 4.64 % less than alkali texturing.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.11 no.6
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• pp.48-54
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• 2012

In recent years, developments in the semiconductor and electronic industries have brought a rapid increase in the use of large size silicon. However, for many companies, it is hard to produce 400mm or 450mm wafers, because of excesive funds for exchange the equipments. Therefore, it is necessary to investigate 300mm wafer to obtain a better efficiency and a good property rate. Polishing is one of the important methods in manufacturing of Si wafers and in thinning of completed device wafers. This research investigated the surface characteristics that apply variable machining conditions and Taguchi Method was used to obtain more flexible and optimal condition. In this study, the machining conditions have head speed, oscillation speed and polishing time. By using optimum condition, it achieves a ultra precision mirror like surface.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2002.11a
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• pp.117-119
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• 2002

A semiconductor cleaning technology has been based upon RCA cleaning which consumes vast amounts of chemicals and ultra pure water. This technology hence gives rise to many environmental issues, and some alternatives such as electrolyzed water are being studied. In this work, intentionally contaminated Si wafers were cleaned using the electrolyzed water. The electrolyzed waters were obtained in anode and cathode with oxidation reduction potentials and pH of -1050mV and 4.8, and -750mV and 10.0, respectively. The electrolyzed water deterioration was correlated with $CO_2$ concentration changes dissolved from air. Overflowing of electrolyzed water during cleaning particles resulted in the same cleanness as could be obtained with RCA clean. The roughness of patterned wafer surfaces after EW clean maintained that of as-received wafers. RCA clean consumed about $9\ell$ chemicals, while electrolyzed water clean did only $400m\ell$ HCl or $600m\ell$ $NH_4$Cl to clean 8" wafers in this study. It was hence concluded that electrolyzed water cleaning technology would be very effective for releasing environment, safety, and health(ESH) issues in the next generation semiconductor manufacturing.ring.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.3
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• pp.177-182
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• 2013

Transparent thin film transistors (TTFT) were fabricated on $N^+$ Si wafers. $SiO_2$, $Si_3N_4/SiO_2$ and $Al_2O_3/SiO_2$ grown on the wafers were used as gate insulators. The rf magnetron sputtered zinc tin oxide (ZTO) films were adopted as active layers. $N^+$ Si wafers were wet-oxidized to grow $SiO_2$. $Si_3N_4$ and $Al_2O_3$ films were deposited on the $SiO_2$ by plasma enhanced chemical vapor deposition (PECVD) and atomic layer deposition (ALD), respectively. The mobility, $I_{on}/I_{off}$ and subthreshold swing (SS) were obtained from the transfer characteristics of TTFTs. The properties of gate insulators were analyzed by comparing the characteristics of TTFTs. The property variation of the ZTO TTFTs with time were observed.

• Journal of the Semiconductor & Display Technology
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• v.17 no.3
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• pp.59-64
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• 2018

In recent years, the solar cell market has steadily grown with the demand for new energies. And wire sawing is one of the most critical processes in manufacturing solar cell wafer which is supposed to affect the breakage of wafers most during the process and afterwards. Generally, the defects of the wafers are generated from the structural vibrations of the machine. In the sawing process, the vibrations cause unnecessary normal stress on the cut surface of wafers, and eventually create the surface damage or leave the residual stress. In this study, the dynamic properties of a wire saw have been analyzed through the frequency response test and the computer simulation. And the effects of the design alterations have been investigated to stabilize the machine structure and further to reduce the vibrations. The result shows that relatively simple design alterations of supporting structure without any change of major parts of the machine can suppress the vibrations of the machine effectively.

• Journal of the Semiconductor & Display Technology
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• v.21 no.2
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• pp.51-56
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• 2022

Recently, the demand for semiconductors is expanded to various industries, and the use of high-quality and high-performance chips is increasing. With the trend, the diameter magnification and high integration of the semiconductor wafers are mandatory. As a result, there is a growing demand for the productivity improvement and the surface precision. There have been many studies on the stabilization of the wafer manufacturing processes in order to satisfy those specifications. Many complaints have been appealed by the wafer buyers that there are many unacceptable wafers with surface defects and foreign material adhesion which are caused by the vibrations during transportation. This study intends to derive the material improvement of the packing box of the wafers to suppress the vibrations of the box, and eventually to reduce the surface defects and the foreign material adhesion. The result shows that optimal material can substantially decrease the vibration of the packing box.