• Journal of Sensor Science and Technology
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• v.16 no.5
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• pp.325-330
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• 2007

For the application to optic devices, wafer level package including spacer with particular thickness according to optical design could be required. In these cases, the uniformity of spacer thickness is important for bonding strength and optical performance. Packaging process has to be performed at low temperature in order to prevent damage to devices fabricated before packaging. And if photosensitive material is used as spacer layer, size and shape of pattern and thickness of spacer can be easily controlled. This paper presents polymer bonding using thick, uniform and patterned spacing layer of SU-8 2100 photoresist for wafer level package. SU-8, negative photoresist, can be coated uniformly by spin coater and it is cured at $95^{\circ}C$ and bonded well near the temperature. It can be bonded to silicon well, patterned with high aspect ratio and easy to form thick layer due to its high viscosity. It is also mechanically strong, chemically resistive and thermally stable. But adhesion of SU-8 to glass is poor, and in the case of forming thick layer, SU-8 layer leans from the perpendicular due to imbalance to gravity. To solve leaning problem, the wafer rotating system was introduced. Imbalance to gravity of thick layer was cancelled out through rotating wafer during curing time. And depositing additional layer of gold onto glass could improve adhesion strength of SU-8 to glass. Conclusively, we established the coating condition for forming patterned SU-8 layer with $400{\mu}m$ of thickness and 3.25 % of uniformity through single coating. Also we improved tensile strength from hundreds kPa to maximum 9.43 MPa through depositing gold layer onto glass substrate.

• Journal of the Semiconductor & Display Technology
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• v.1 no.1
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• pp.15-19
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• 2002

A new vacuum packaging process in wafer level is developed for the surface micromachining devices using glass silicon anodic bonding technology. The inside pressure of the packaged device was measured indirectly by the quality factor of the mechanical resonator. The measured Q factor was about 5$\times10^4$ and the estimated inner pressure was about 1 mTorr. And it is also possible to change the inside pressure of the packaged devices from 2 Torr to 1 mTorr by varying the amount of the Ti gettering material. The long-term stability test is still on the way, but in initial characterization, the yield is about 80% and the vacuum degradation with time was not observed.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.53-58
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• 2018

Since the scaling-down of IC devices has been reached to their physical limitations, several innovative packaging technologies such as 3D packaging, embedded packaging, and fan-out wafer level packaging (FOWLP) are actively studied. In this study the fabrication of organic-inorganic dielectric material was evaluated for the use of multi-structured redistribution layers (RDL) in FOWLP. Compared to current organic dielectrics such as PI or PBO an organic-inorganic hybrid dielectric called polysilsesquioxane (PSSQ) can improve mechanical, thermal, and electrical stabilities. polysilsesquioxane has also an excellent advantage of simultaneous curing and patterning through UV exposure. The polysilsesquioxane samples were fabricated by spin-coating on 6-inch Si wafer followed by pre-baking and UV exposure. With the 10 minutes of UV exposure polysilsesquioxane was fully cured and showed $2{\mu}m$ line-pattern formation. And the dielectric constant of cured polysilsesquioxane dielectrics was ranged from 2.0 to 2.4. It has been demonstrated that polysilsesquioxane dielectric can be patterned and cured by UV exposure alone without a high temperature curing process.

• Electrical & Electronic Materials
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• v.34 no.2
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• pp.4-11
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• 2021

• Journal of the Microelectronics and Packaging Society
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• v.20 no.1
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• pp.7-13
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• 2013

3D stacked IC is one of the promising candidates which can keep Moore's law valid for next decades. IC can be stacked through various bonding technologies and they were reviewed in this report, for example, wafer direct bonding and atomic diffusion bonding, etc. As an effort to reduce the high temperature and pressure which were required for high bonding strength in conventional Cu-Cu thermo-compression bonding, surface activated bonding, solid liquid inter-diffusion and direct bonding interface technologies are actively being developed.

• Journal of Sensor Science and Technology
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• v.31 no.1
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• pp.36-40
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• 2022

High-power devices, such as LEDs and radars, inevitably generate a large amount of heat, which is the main cause of shortening lifespan, deterioration in performance, and failure of electronic devices. The embedded IC process can be a solution; however, when applied to large-area substrates (larger than 8 in), there is a limit owing to the difficulty in the process after wafer thinning. In this study, an 8-in wafer-level high-power electronic package based on the embedded IC process was implemented with temporary bonding and debonding technology using double-sided thermal release tape. Good heat-dissipation characteristics were demonstrated both theoretically and experimentally. These findings will advance the commercialization of high-power electronic packaging.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.19-25
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• 2000

Dielectric polymer films produced from benzocyclobutene (BCB) formulations (CYCLOTENE＊ family resins) are known to possess many desirable properties for microelectronic applications; for example, low dielectric constant and dissipation factor, low moisture absorption, rapid curing on hot plate without reaction by-products, minimum shrinkage in curing process, and no Cu migration issues. Recently, BCB-based products for thick film applications have been developed, which exhibited excellent dissipation factor and dielectric constant well into the GHz range, 0.002 and 2.50, respectively. Derived from these properties, the applications are developed in: bumping/wafer level packaging, Ga/As chip ILD, optical waveguide, flat panel display, and lately in BCB-coated Cu foil for build-up board. In this paper, we review the relevant properties of BCB, then the application areas in bumping/wafer level packaging and BCB-coated Cu foil for build-up board.

• Journal of the Semiconductor & Display Technology
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• v.18 no.1
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• pp.65-69
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• 2019

The cure properties of ethoxysilyl diglycidyl isocyanurate(Ethoxysilyl-DGIC) and ethylsilyl diglycidyl isocyanurate (Ethylsilyl-DGIC) epoxy resin systems with a phenol novolac hardener were investigated for anticipating fan out-wafer level package(FO-WLP) applications, comparing with ethoxysilyl diglycidyl ether of bisphenol-A(Ethoxysilyl-DGEBA) epoxy resin systems. The cure kinetics of these systems were analyzed by differential scanning calorimetry with an isothermal approach, and the kinetic parameters of all systems were reported in generalized kinetic equations with diffusion effects. The isocyanurate type epoxy resin systems represented the higher cure conversion rates comparing with bisphenol-A type epoxy resin systems. The Ethoxysilyl-DGIC epoxy resin system showed the highest cure conversion rates than Ethylsilyl-DGIC and Ethoxysilyl-DGEBA epoxy resin systems. It can be figured out by kinetic parameter analysis that the highest conversion rates of Ethoxysilyl-DGIC epoxy resin system are caused by higher collision frequency factor. However, the cure conversion rate increases of the Ethylsilyl-DGEBA comparing with Ethoxysilyl-DGEBA are due to the lower activation energy of Ethylsilyl-DGIC. These higher cure conversion rates in the isocyanurate type epoxy resin systems could be explained by the improvements of reaction molecule movements according to the compact structure of isocyanurate epoxy resin.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.10a
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• pp.479-480
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• 2012

• Journal of the Microelectronics and Packaging Society
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• v.26 no.1
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• pp.29-33
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• 2019

With shrinking form factor and improving performance of electronic packages, high input/output (I/O) density is considered as an important factor. Fan out wafer-level packaging (FO-WLP) has been paid great attention as an alternative. However, FO-WLP is vulnerable to warpage during its manufacturing process. Minimizing warpage is essential for controlling production yield, and in turn, package reliability. While many studies investigated the effect of process and design parameters on warpage using finite element analysis, they did not take uncertainty into consideration. As parameters, including material properties, chip positions, have uncertainty from the point of manufacturing view, the uncertainty should be considered to reduce the gap between the results from the field and the finite element analysis. This paper focuses on the effect of uncertainty of Young's modulus of chip on fan-out wafer level packaging warpage using finite element analysis. It is assumed that Young's modulus of each chip follows the normal distribution. Simulation results show that the uncertainty of Young's modulus affects the maximum von Mises stress. As a result, it is necessary to control the uncertainty of Young's modulus of silicon chip since the maximum von Mises stress is a parameter related to the package reliability.