• Industrial Engineering and Management Systems
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• v.2 no.1
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• pp.9-27
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• 2003

In a wafer fabrication factory, the completion time of an order is affected by many factors related to the specifics of the order and the status of the system, so is difficult to predict precisely. The level of influence of each factor on the order completion time may also depend on the production system characteristics, such as the rules for releasing and dispatching. This paper presents a method to identify those factors that significantly impact upon the order completion time under various combinations of scheduling rules. Computer simulations and statistical analyses were used to develop effective due date assignment models for improving the due date related performances. The first step of this research was to select the releasing and dispatching rules from those that were cited so frequently in related wafer fabrication factory researches. Simulation and statistical analyses were combined to identify the critical factors for predicting order completion time under various combinations of scheduling rules. In each combination of scheduling rules, two efficient due date assignment models were established by using the regression method for accurately predicting the order due date. Two due date assignment models, called the significant factor prediction model (SFM) and the key factor prediction model (KFM), are proposed to empirically compare the due date assignment rules widely used in practice. The simulation results indicate that SFM and KFM are superior to the other due date assignment rules. The releasing rule, dispatching rule and due date assignment rule have significant impacts on the due date related performances, with larger improvements coming from due date assignment and dispatching rules than from releasing rules.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.9
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• pp.5748-5755
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• 2015

Scribing is cutting process to determine production amount and characteristic of LED chip. So it is an important process for fabrication of LED chip. Mechanical process and conventional scribing process with laser source has several problems such as thermal deformation, decreasing of material strength and limitation of cutting region. To solve these problems, internal laser scribing process that generates void in wafer and derives self-crack has been researched. However, studies of sapphire wafer cutting by internal laser scribing process for fabrication of LED chip are still insufficient. In this paper, cutting parameters were determined to apply internal laser scribing process for sapphire wafer for fabrication of LED chip. Then, foundation of cutting condition was established to set up internal laser scribing system through investigation of cutting characteristics by several experiments.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.629-632
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• 1998

This paper presents a new and simple technique to realize high Q inductor on low resistivity silicon wafer with 6 $\Omega$.cm. This technique is very compatible with bipolar and CMOS standard silicon process. By forming the deep and narrow trenches on the low resistivity wafer substrate under inductor pattern, oxidizing and filling with undoped polysilicon, the low resistivity silicon wafer acts as high resistivity wafer being suitable for the fabrication of high Q inductor. By using this technique the quality factor (Q) for 8-turn spiral inductor was improved up to max. 10.3 at 2 ㎓ with 3.0 $\mu\textrm{m}$ of metal thickness. The experiment results show that Q on low resistivity silicon wafer with the trench technique have been improved more than 2 times compared to the conventional low resistivity silicon wafer without trenches.

• Journal of the Semiconductor & Display Technology
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• v.19 no.2
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• pp.77-81
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• 2020

Silicon wafer etching in micro electro mechanical systems (MEMS) fabrication is challenging to form 3-D structures. Well known Si-wet etch of silicon employs potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH) and sodium hydroxide (NaOH). However, the existing silicon wet etching process has a fatal disadvantage that etching of the back side of the wafer is hard to avoid. In this study, a wet etching bath for 150 mm wafers was designed to prevent back-side etching of silicon wafer, and we demonstrated the optimized process recipe to have anisotropic wet etching of silicon wafer without any damage on the backside. We also presented the design of wet bath for 300 mm wafer processing as a promising process development.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.2 s.95
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• pp.60-67
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• 1999

Micro-fabrication techniques such as lithography and LIGA processes usually require large investment and are suitable for mass production. Therefore, there is a need for a new micro-fabrication technique that is flexible and more cost effective. In this paper a novel, economical and flexible method of producing micro-pattern on silicon wafer is presented. This method relies on selective removal of mask by mechanical cutting. Then micro-pattern is produced by chemical etching. V-shaped grooved of about 3 ${\mu}m$ wide and 2 ${\mu}m$ deep has been made on ${SiO_2}m$ coated silicon wafer with this method. This method may be utilized for making microstructures in MEMS application at low cost.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.43-49
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• 2013

We have studied on ozonate water cleaning mechanisms to apply in manufacturing process of 156 mm silicon wafer which is used in the solar cell fabrication. We have analyzed contamination sources on wafer surface which causes poor quality and performance of products in fabrication process, and examined cleaning process using ozonate water to eliminate it. Using this novel technology particles are removed over 94%, and remained organic materials are removed more over 45%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.13-20
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• 2008

This paper describes the methods of spacer-fabrication for wafer-level CIS(CMOS Image Sensor) assembly. We propose three methods using SU-8, PDMS and Si-interposer for the spacer-fabrication. For SU-8 spacer, novel wafer rotating system is developed and for PDMS(poly-dimethyl siloxane) spacer, new fabrication-method is used to bond with alignment of glass/PDMS/glass structure. And for Si-interposer, DFR(Dry Film Resist) is used as adhesive layer. The spacer using Si-interposer has the strongest bonding strength and the strength is 32.3MPa with shear.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.05a
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• pp.381-382
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• 2012

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.05a
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• pp.535-536
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• 2012

• Journal of the Korea Society for Simulation
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• v.12 no.3
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• pp.13-20
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• 2003

Semiconductor Manufacturing has emerged as one of the most important world industries. Even with the highly automated and precisely monitored facilities used to process the complex manufacturing steps in a near particle free environment, processing variations in wafer fabrication still exist. The causes of these variations may arise from equipment malfunctions, delicate and difficult processing steps, or human mistakes. In this paper, we could specify the cause stage and the cause equipment and take countermeasures at a speed by the conventional method, without depending on the experience and skills of the engineer