• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1921-1923
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• 2001

In this work, an array of resistance temperature detector(RTD) was fabricated inside the microchannel in order to investigate in-situ flow characteristics. A rectangular straight microchannel, integrated with RTD's for temperature sensing and a heat source for generating the temperature gradient along the channel. were fabricated with the dimension of $200{\mu}m(W){\times}{\mu}m(D){\times}$48mm(L), while RTD measured precise temperatures at the inside-channel wall. 4" $525{\pm}25{\mu}m$ thick P-type <100> Si wafer was used as a substrate. For the fabrication of RTDs. 5300$\AA$ thick Pt/Ti layer was sputtered on a Pyrex glass wafer. Finally, glass wafer was bonded with Si wafer by anodic bonding, therefore RTD was located inside the microchannel. The temperature distribution inside the fabricated microchannel was obtained from 4 point probe measurements and Dl water is used as a working fluid. Temperature distribution inside the microchannel was measured as a function of mass flow rate and heat flux. As a result, precise temperatures inside the microchannel could be obtained. In conclusion, this novel temperature distribution measurement system will be very useful to the accurate analysis of the flow characteristics in the microchannel.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.2
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• pp.29-36
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• 2008

In this paper, mechanical reliability issues of copper through-wafer interconnections are investigated numerically and experimentally. A hermetic wafer level packaging for MEMS devices is developed. Au-Sn eutectic bonding technology is used to achieve hermetic sealing, and the vertical through-hole via filled with electroplated copper for the electrical connection is also used. The MEMS package has the size of $1mm{\times}1mm{\times}700{\mu}m$. The robustness of the package is confirmed by several reliability tests. Several factors which could induce via hole cracking failure are investigated such as thermal expansion mismatch, via etch profile, and copper diffusion phenomenon. Alternative electroplating process is suggested for preventing Cu diffusion and increasing the adhesion performance of the electroplating process. After implementing several improvements, reliability tests were performed, and via hole cracking as well as significant changes in the shear strength were not observed. Helium leak testing indicated that the leak rate of the package meets the requirements of MIL-STD-883F specification.

• Proceedings of the KWS Conference
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• 2005.06a
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• pp.54-56
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• 2005

Ultrasonic soldering using of Si-wafer to FR-4 PCB atroom temperature was investigated. Sn3.5Ag foil rolled $100{\mu}m$ was used for solder. The UBM of Si-die was Cu/ Ni/ Al from top to bottom and its thickness was $0.4{\mu}m$, $0.4{\mu}m$, $0.3{\mu}m$ respectively. Pad on FR-4 PCB comprised of Au/ Ni/ Cu from top to bottom and its thickness was $0.05{\mu}m$, $5{\mu}m$, $18{\mu}m$ respectively. The ultrasonic soldering time was changed from 0.5sec to 3.0sec and its power 1400W. As experimental result, reliable bond joint by ultrasonic at room temperature was obtained. The shear strength increased with soldering time up to 2.5 sec. That means at 2.5sec, the shear strength showed maximum rate of 65.23N. The strength decreased to 33.90N at 3.0 sec because the cracks generated along the intermetallic compound between Si-wafer and Sn-3.5mass%Ag solder. intermetallic compound produced by ultrasonic between the solder and the Si-die was $(Cu, Ni)_{6}Sn_{5}$ and the intermetallic compound between solder and pad on FR-4 was $(Ni, Cu)_{3}Sn_{4}$.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.9
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• pp.449-454
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• 2002

A rectangular straight microchannel, integrated with the resistance temperature detectors(RTDs) for temperature sensing and a micro-heater for generating the Temperature gradient along the channel, was fabricated. Its dimension is 57${\mu}{\textrm}{m}$(H)$\times$200${\mu}{\textrm}{m}$(W)$\times$48,050${\mu}{\textrm}{m}$(L), and RTDs were placed at the inner-channel wall. Si wafer was used as a substrate. For the fabrication of RTDs, 5300$\AA$ thick Pt/Ti layer was sputtered on a Pyrex glass wafer. Finally, the glass wafer was bonded with Si wafer by anodic bonding, so that the RTDs are located inside the microchannel. Temperature coefficient of resistance(TCR) values of the fabricated Pt-RTDs were 2800~2950ppm$^{\circ}C$ and the variation of TCR value In the range of O~10$0^{\circ}C$ was less than 0.3％. Therefore, it was proved that the fabricated Pt-RTDs without annealing were excellent as temperature sensors. The temperature distribution in the microchannel was investigated as a function of mass flow rate and heating power. The temperature increase rate diminished with decreasing the applied power and increasing the mass flow rate. It was confirmed from the comparison with the simulation results that the temperature measured inside the microchannel is more accurate than measuring the temperature measured at the outer wall. The proposed temperature sensing method and microchannel are expected to be useful in microfluidics researches.

• Publications of The Korean Astronomical Society
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• v.32 no.1
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• pp.351-353
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• 2017

To realize large-format compact array detectors covering a wide far-infrared wavelength range up to 200 µm, we have been developing Blocked-Impurity-Band (BIB) type Ge detectors with the room-temperature surface-activated wafer bonding technology provided by Mitsubishi Heavy Industries. We fabricated various types of $p^+-i$ junction devices which possessed a BIB-type structure, and evaluated their spectral response curves using a Fourier transform spectrometer. From the Hall effect measurement, we also obtained the physical characteristics of the $p^+$ layers which constituted the $p^+-i$ junction devices. The overall result of our measurement shows that the $p^+-i$ junction devices have a promising applicability as a new far-infrared detector to cover a wavelength range of $100-200{\mu}m$.

• The Korean Journal of Ceramics
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• v.7 no.1
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• pp.36-40
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• 2001

In order to fabricate uncooled IR sensors for pyroelectric applications, multilayered thin films of Pt/PbTiO$_3$/Pt/Ti/Si$_3$N$_4$/SiO$_2$/Si and thermally isolating membrane structures of square-shaped/cantilevers-shaped microstructures were prepared. Cavity was also fabricated via direct silicon wafer bonding and etching technique. Metallic Pt layer was deposited by ion beam sputtering while PbTiO$_3$ thin films were prepared by sol-gel technique. Micromachining technology was used to fabricate microstructured-membrane detectors. In order to avoid a difficulty of etching active layers, silicon-nitride membrane structure was fabricated through the direct bonding and etching of the silicon wafer. Although multilayered thin film deposition and device fabrications were processed independently, these could b integrated to make IR micro-sensor devices.

• Advances in nano research
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• v.2 no.1
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• pp.1-14
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• 2014

Dislocations are basic crystal defects and represent one-dimensional native nanostructures embedded in a perfect crystalline matrix. Their structure is predefined by crystal symmetry. Two-dimensional, self-organized arrays of such nanostructures are realized reproducibly using specific preparation conditions (semiconductor wafer direct bonding). This technique allows separating dislocations up to a few hundred nanometers which enables electrical measurements of only a few, or, in the ideal case, of an individual dislocation. Electrical properties of dislocations in silicon were measured using MOSFETs as test structures. It is shown that an increase of the drain current results for nMOSFETs which is caused by a high concentration of electrons on dislocations in p-type material. The number of electrons on a dislocation is estimated from device simulations. This leads to the conclusion that metallic-like conduction exists along dislocations in this material caused by a one-dimensional carrier confinement. On the other hand, measurements of pMOSFETs prepared in n-type silicon proved the dominant transport of holes along dislocations. The experimentally measured increase of the drain current, however, is here not only caused by an higher hole concentration on these defects but also by an increasing hole mobility along dislocations. All the data proved for the first time the ambipolar behavior of dislocations in silicon. Dislocations in p-type Si form efficient one-dimensional channels for electrons, while dislocations in n-type material cause one-dimensional channels for holes.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.4
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• pp.91-96
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• 2014

Through silicon via (TSV) technology is to form a via hole in a silicon chip, and to stack the chips vertically for three-dimensional (3D) electronics packaging technology. This can reduce current path, power consumption and response time. In this study, Cu-filling substrate size was changed from Si-chip to a 4" wafer to investigate the behavior of Cu filling in wafer level. The electrolyte for Cu filling consisted of $CuSO_4$ $5H_2O$, $H_2SO_4$ and small amount of additives. The anode was Pt, and cathode was changed from $0.5{\times}0.5cm^2$ to 4" wafer. As experimental results, in the case of $5{\times}5cm^2$ Si chip, suitable distance of electrodes was 4cm having 100% filling ratio. The distance of 0~0.5 cm from current supplying location showed 100% filling ratio, and distance of 4.5~5 cm showed 95%. It was confirmed good TSV filling was achieved by plating for 2.5 hrs.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.3
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• pp.9-15
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• 2021

Miniaturization of semiconductor devices has recently faced a physical limitation. To overcome this, 3D packaging in which semiconductor devices are vertically stacked has been actively developed. 3D packaging requires three unit processes of TSV, wafer grinding, and bonding, and among these, copper bonding is becoming very important for high performance and fine-pitch in 3D packaging. In this study, the effects of Ti nanolayer on the antioxidation of copper surface and low-temperature Cu bonding was investigated. The diffusion rate of Ti into Cu is faster than Cu into Ti in the temperature ranging from room temperature to 200℃, which shows that the titanium nanolayer can be effective for low-temperature copper bonding. The 12nm-thick titanium layer was uniformly deposited on the copper surface, and the surface roughness (R_q) was lowered from 4.1 nm to 3.2 nm. Cu bonding using Ti nanolayer was carried out at 200℃ for 1 hour, and then annealing at the same temperature and time. The average shear strength measured after bonding was 13.2 MPa.

• Korean Journal of Materials Research
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• v.11 no.5
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• pp.427-430
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• 2001

We prepared 10cm-diameter Si(100)/500 $\AA$-Si$_3$N$_4$/Si(100) wafer Pairs adopting 500 $\AA$ -thick Si$_3$N$_4$layer as insulating layer between single crystal Si wafers. Si3N, is superior to conventional SiO$_2$ in insulating. We premated a p-type(100) Si wafer and 500 $\AA$ -thick LPCVD Si$_3$N$_4$∥Si (100) wafer in a class 100 clean room. The cremated wafers are separated in two groups. One group is treated to have hydrophobic surface and the other to have hydrophilic. We employed a FLA(fast linear annealing) bonder to enhance the bond strength of cremated wafers at the scan velocity of 0.1mm/sec with varying the heat input at the range of 400~1125W. We measured bonded area using a infrared camera and bonding strength by the razor blade crack opening method. We used high resolution transmission electron microscopy(HRTEM) to probe cross sectional view of bonded wafers. The bonded area of two groups was about 75%. The bonding strength of samples which have hydrophobic surface increased with heat input up to 1577mJ/$m^2$ However, bonding strength of samples which have hydrophilic surface was above 2000mJ/$m^2$regardless of heat input. The HRTEM results showed that the hydrophilic samples have about 25 $\AA$ -thick SiO layer between Si and Si$_3$N$_4$/Si and that maybe lead to increase of bonding strength.