• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.176-183
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• 2017

There is a problem of long erase and program times in testing large-density memories. Also, there is a need of testing the VT voltages of EEPROM cells at each step during the reliability test. In this paper, a cell verification module is designed for a 512kb EEPROM and a CG (control gate) driver is proposed for measuring the VT voltages of a split gate EEPROM having negative erase VT voltages. In the proposed cell verification module, asymmetric isolated HV (high-voltage) NMOS devices are used to apply negative voltages of -3V to 0V in measuring erase VT voltages. Since erasing and programming can be done in units of even pages, odd pages, or a chip in the test time reduction mode, test time can be reduced to 2ms in testing the chip from 4ms in testing the even and the odd pages.

• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.179-180
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• 2011

This paper focuses on the Current-Voltage concurrent control method devoted to the multiple LED (light-emitting diode) string driver. Isolated DC to DC converter with cascaded chopping switch is proposed for smart lighting system such as light with sensor or back light unit of display, which need to control the current of parallel connected multiple LED stings and regulate DC voltage for micro controller for brightness control. The proposed circuit regulates the current of parallel connected multiple LED strings and additional DC voltage output simultaneously. To verify the performance, experimental results are presented based on the prototype board. 5V, 1A voltage mode electric load and two LED strings with different forward voltages are used for output loads. 23W output power is achieved and measured efficiency is in the range of 85%-87%

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.4
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• pp.71-78
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• 2005

This paper proposes a novel multi-level energy recovery sustaining driver for AC PDP(Plasma Display Panel), which solves the problems of the conventional multi-level sustaining driver. While the conventional circuit improves the voltage md current stress of the switching elements in Weber circuit not only there are parasitic resonant currents between resonant inductors and parasitic capacitance and hard switching, but also the changing period between 0 and sustain voltage is too long. Comparing the proposed circuit with the conventional circuit, the number of components are reduced and the parasitic resonant currents in resonant inductors are eliminated Moreover the hard switching problem is solved by using CIM(Current Injection Method) and the operating frequency will be high as much as possible by removing Vs/2 sustain period. And the circuit operations of the proposed circuit are analyzed for each mode and the validity is verified by the simulations using PSpice program.

• ETRI Journal
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• v.27 no.1
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• pp.81-88
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• 2005

In this paper, interface circuits that are suitable for point-to-point interconnection with an over 1 Gbps data rate per pin are proposed. To achieve a successful data transfer rate of multi-gigabits per-second between two chips with a point-to-point interconnection, the input receiver uses an on-chip parallel terminator of the pass gate style, while the output driver uses the pullup and pulldown transistors of the diode-connected style. In addition, the novel dynamic voltage level converter (DVLC) has solved such problems as the access time increase and valid data window reduction. These schemes were adopted on a 64 Mb DDR SRAM with a 1.5 Gbps data rate per pin and fabricated using a 0.10 ${\mu}m$ dual gate oxide CMOS technology.

• ETRI Journal
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• v.36 no.3
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• pp.352-360
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• 2014

This paper presents a 900 MHz zero-IF RF transceiver for IEEE 802.15.4g Smart Utility Networks OFDM systems. The proposed RF transceiver comprises an RF front end, a Tx baseband analog circuit, an Rx baseband analog circuit, and a ${\Delta}{\Sigma}$ fractional-N frequency synthesizer. In the RF front end, re-use of a matching network reduces the chip size of the RF transceiver. Since a T/Rx switch is implemented only at the input of the low noise amplifier, the driver amplifier can deliver its output power to an antenna without any signal loss; thus, leading to a low dc power consumption. The proposed current-driven passive mixer in Rx and voltage-mode passive mixer in Tx can mitigate the IQ crosstalk problem, while maintaining 50% duty-cycle in local oscillator clocks. The overall Rx-baseband circuits can provide a voltage gain of 70 dB with a 1 dB gain control step. The proposed RF transceiver is implemented in a $0.18{\mu}$ CMOS technology and consumes 37 mA in Tx mode and 38 mA in Rx mode from a 1.8 V supply voltage. The fabricated chip shows a Tx average power of -2 dBm, a sensitivity level of -103 dBm at 100 Kbps with PER < 1%, an Rx input $P_{1dB}$ of -11 dBm, and an Rx input IP3 of -2.3 dBm.

• Journal of Electrical Engineering and Technology
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• v.8 no.1
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• pp.137-143
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• 2013

This paper presents development of variable speed generation (VSG) system with energy saving function. The rubber tyred gantry crane (RTGC) requires the power from diesel-engine. Significant fuel savings by reducing the engine speed can be achieved, because all of operation modes except hoisting are required lower power than rated value of engine. When low speed operation output voltage of generator is decrease until acceptable range of motor driver inverters and auxiliary load supplier. According to power demand engine speed is varying from 20 to 60Hz, and voltage is varying between 210Vac and 480Vac. When idle mode or low power operation dc/dc converter operates by constant output voltage control and inverters dc site voltage is compensated by it. This paper proposed 3-phase interleaved boost converter which has the same structure as the commercially available 3-phase inverter and current sharing capability. 400kW interleaved converter is designed and a performance of converter is evaluated through several experiments with a RTGC system. Energy saving VSG system can cut down fuel consumption by 36% and 21.3% at idle and unidirectional load operations.

• The Transactions of the Korean Institute of Power Electronics
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• v.11 no.6
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• pp.494-501
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• 2006

In this paper, a novel energy recovery circuit for AC PDPs(Plasma Display Panels) with reduced sustain voltage is proposed to improve the performance of conventional circuits such as TERES(TEchnology of REciprocal Sustainer). In the TERES circuit, the sustain voltage is the half of general sustaining driver for AC PDPs, however, there is no energy recovery circuit. In the proposed circuit, the efficiency is heightened by installing in energy recovery circuit and the loss of switching device is reduced by performing the zero voltage switching or zero current switching. Although the energy recovery circuit is added, the number of active switching elements of the proposed circuit is the same as that of the TERES circuit. The operations of the proposed circuit are analyzed for each mode and its validity is verified by the simulations and experimentation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.2
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• pp.85-90
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• 2009

This paper presents a single supply PLC SoC ASIC with a built-in analog Front-end circuit. To achieve the low power consumption along with low cost, this PLC SoC employs fully CMOS Analog Front End (AFE) and several LDO regulators (LDOs) to provide the internal power for Logic Core, DAC and Input/output Pad driver. The receiver part of the AFE consists of Pre-amplifier, Gain Amplifier and 1 bit Comparator. The transmitter part of the AFE consists of 10 bit Digital Analog Converter and Line Driver. This SoC is implemented with 0.18 ${\mu}m$ 1 Poly 5 Metal CMOS Process. The single supply voltage is 3.3 V and the internal powers are provided using LDOs. The total power consumption is below 30 mA at stand-by mode to meet the Eco-Design requirement. The die size is 3.2 $\times$ 2.8 $mm^{2}$.

• ETRI Journal
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• v.42 no.5
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• pp.773-780
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• 2020

A 40 nm complementary metal oxide semiconductor carrier-aggregated drive amplifier with high linearity is presented for sub-GHz Internet of Things applications. The proposed drive amplifier consists of two high linear amplifiers, which are composed of five differential cascode cells. Carrier aggregation can be achieved by switching on both the driver amplifiers simultaneously and combining the two independent signals in the current mode. The common gate bias of the cascode cells is selected to maximize the output 1 dB compression point (P1dB) to support high-linear wideband applications, and is used for the local supply voltage of digital circuitry for gain control. The proposed circuit achieved an output P1dB of 10.7 dBm with over 22.8 dBm of output 3rd-order intercept point up to 0.9 GHz and demonstrated a 55 dBc adjacent channel leakage ratio (ACLR) for the 802.11af with -5 dBm channel power. To the best of our knowledge, this is the first demonstration of the wideband carrier-aggregated drive amplifier that achieves the highest ACLR performance.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.423-424
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• 2011

This paper has proposed a 920 MHz RF front-end for IEEE 802.15.4g SUN (Smart Utility Network) systems. The proposed 920 MHz RF front-end consists of a driver amplifier, a low noise amplifier, and a RF switch. In the TX mode, the driver amplifier has been designed as a single-ended topology to remove a transformer which causes a loss of the output power from the driver amplifier. In addition, a RF switch is located in the RX path not the TX path. In the RX mode, the proposed low noise amplifier can provide a differential output signal when a single-ended input signal has been applied to. A LC resonant circuit is used as both a load of the drive amplifier and a input matching circuit of the low noise amplifier, reducing the chip area. The proposed 920 MHz RF Front-end has been implemented in a 0.18-um CMOS technology. It consumes 3.6 mA in driver amplifier and 3.1 mA in low noise amplifier from a 1.8 V supply voltage.